From mboxrd@z Thu Jan 1 00:00:00 1970 From: Andrew Cooper Subject: Re: [PATCH V3 2/6] x86/xsaves: enable xsaves/xrstors in xen Date: Wed, 5 Aug 2015 18:57:46 +0100 Message-ID: <55C24E9A.9080403@citrix.com> References: <1438739842-31658-1-git-send-email-shuai.ruan@linux.intel.com> <1438739842-31658-3-git-send-email-shuai.ruan@linux.intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <1438739842-31658-3-git-send-email-shuai.ruan@linux.intel.com> List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org To: Shuai Ruan , xen-devel@lists.xen.org Cc: kevin.tian@intel.com, wei.liu2@citrix.com, Ian.Campbell@citrix.com, stefano.stabellini@eu.citrix.com, eddie.dong@intel.com, ian.jackson@eu.citrix.com, jbeulich@suse.com, jun.nakajima@intel.com, keir@xen.org List-Id: xen-devel@lists.xenproject.org On 05/08/15 02:57, Shuai Ruan wrote: > This patch uses xsaves/xrstors instead of xsaveopt/xrstor > to perform the xsave_area switching so that xen itself > can benefit from them when available. > > Please note that xsaves/xrstors only use compact format. > > Signed-off-by: Shuai Ruan > --- > xen/arch/x86/i387.c | 5 ++++ > xen/arch/x86/xstate.c | 70 +++++++++++++++++++++++++------------------- > xen/include/asm-x86/xstate.h | 4 ++- > 3 files changed, 48 insertions(+), 31 deletions(-) > > diff --git a/xen/arch/x86/i387.c b/xen/arch/x86/i387.c > index 14f2a79..9071374 100644 > --- a/xen/arch/x86/i387.c > +++ b/xen/arch/x86/i387.c > @@ -309,7 +309,12 @@ int vcpu_init_fpu(struct vcpu *v) > return rc; > > if ( v->arch.xsave_area ) > + { > v->arch.fpu_ctxt = &v->arch.xsave_area->fpu_sse; > + > + if ( cpu_has_xsaves ) > + v->arch.xsave_area->xsave_hdr.xcomp_bv |= XSTATE_COMPACTION_ENABLED; > + } By making this change, you need to make arch_set_info_guest() able to interpret and unpack a compressed xsave area without hardware support. Otherwise, you have broken migration of PV vcpus between Skylake and non-Skylake hardware. ~Andrew