From: Andrew Cooper <andrew.cooper3@citrix.com>
To: Tim Deegan <tim@xen.org>, Jan Beulich <JBeulich@suse.com>
Cc: Kevin Tian <kevin.tian@intel.com>, Wei Liu <wei.liu2@citrix.com>,
George Dunlap <george.dunlap@eu.citrix.com>,
xen-devel@lists.xen.org, Kai Huang <kai.huang@linux.intel.com>,
Ross Lagerwall <ross.lagerwall@citrix.com>,
Jun Nakajima <jun.nakajima@intel.com>, Keir Fraser <keir@xen.org>
Subject: Re: [PATCH for-4.6] p2m/ept: Set the A bit only if PML is enabled
Date: Thu, 24 Sep 2015 10:13:27 +0100 [thread overview]
Message-ID: <5603BEB7.1030103@citrix.com> (raw)
In-Reply-To: <20150924091003.GA63393@deinos.phlegethon.org>
>> etc along with adjusting the existing gating of PML on AD being
>> available (perhaps by simply stripping the respective bit from what
>> we read from MSR_IA32_VMX_EPT_VPID_CAP). Of course this
>> then ignores the fact that the erratum only affects the A bit, but
>> I think we can live with that.
>>
>> I also think the currently slightly strange setting of the ept_ad bit
>> should be changed: There's no point setting the bit for domains
>> not getting PML enabled (and incurring the overhead of the
>> hardware updating the bits); imo this should instead be done in
>> ept_enable_pml() / vmx_domain_enable_pml() (and undone in
>> the respective disable function).
> Yep.
Just as a note, in the non PML case, the AD enable bit in EPTP is left
clear, which means that the A/D bits in the EPTs have no effect.
Therefore, despite the unconditional setting of the A/D bits, there is
still no MMU overhead.
~Andrew
next prev parent reply other threads:[~2015-09-24 9:13 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-09-16 8:47 [PATCH for-4.6] p2m/ept: Set the A bit only if PML is enabled Ross Lagerwall
2015-09-16 14:46 ` Wei Liu
2015-09-16 15:17 ` Ross Lagerwall
2015-09-16 15:23 ` Wei Liu
2015-09-16 19:47 ` Andrew Cooper
2015-09-21 12:30 ` Jan Beulich
2015-09-21 14:33 ` Tim Deegan
2015-09-23 15:18 ` Wei Liu
2015-09-23 15:28 ` Konrad Rzeszutek Wilk
2015-09-23 15:43 ` George Dunlap
2015-09-23 15:46 ` Tim Deegan
2015-09-24 7:02 ` Jan Beulich
2015-09-24 9:10 ` Tim Deegan
2015-09-24 9:13 ` Andrew Cooper [this message]
2015-09-24 9:20 ` Tim Deegan
2015-09-24 9:41 ` Jan Beulich
2015-09-24 9:33 ` Jan Beulich
2015-09-24 10:45 ` Wei Liu
2015-09-24 10:49 ` Wei Liu
2015-09-28 8:42 ` Kai Huang
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