From mboxrd@z Thu Jan 1 00:00:00 1970 From: Andrew Cooper Subject: Re: [PATCH] x86emul: support clzero Date: Thu, 24 Sep 2015 12:59:01 +0100 Message-ID: <5603E585.2010907@citrix.com> References: <56016E8102000078000A45B7@prv-mh.provo.novell.com> <5602E35B.4060704@citrix.com> <5603CA4C02000078000A51F3@prv-mh.provo.novell.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mail6.bemta14.messagelabs.com ([193.109.254.103]) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1Zf5B5-0001Oz-9P for xen-devel@lists.xenproject.org; Thu, 24 Sep 2015 11:59:07 +0000 In-Reply-To: <5603CA4C02000078000A51F3@prv-mh.provo.novell.com> List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org To: Jan Beulich Cc: xen-devel , Keir Fraser , Aravind Gopalakrishnan , suravee.suthikulpanit@amd.com List-Id: xen-devel@lists.xenproject.org On 24/09/15 09:02, Jan Beulich wrote: >>>> On 23.09.15 at 19:37, wrote: >> On 22/09/15 14:06, Jan Beulich wrote: >>> ... in anticipation of this possibly going to get used by guests for >>> basic thinks like memset() or clearing or pages. >>> >>> Since the emulation doesn't use clzero itself, checking the guest's >>> CPUID for the feature to be exposed is (intentionally) being avoided >>> here. All that's required is sensible guest side data for the clflush >>> line size. >>> >>> Signed-off-by: Jan Beulich >> Where have you found this instruction? Googling, I have found a >> presentation talking about it being new in the new AMD Zen cores, but I >> still can't locate any technical documentation on the matter. > Sadly no technical documentation so far, despite me pinging for it > after the respective binutils patch > (https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;a=commitdiff;h=029f3522619e8b77a7b848be23f4c13e50087d8b) > got posted and went in. While I don't see an obvious issue with your patch, I can't claim to have reviewed it without some documentation to refer to. Aravind/Suravee: Any ideas when the AMD manuals might be updated to include this? ~Andrew