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From: Julien Grall <julien.grall@citrix.com>
To: Ian Campbell <ian.campbell@citrix.com>, xen-devel@lists.xenproject.org
Cc: stefano.stabellini@eu.citrix.com
Subject: Re: [PATCH v3 7/9] xen/arm: vgic: Optimize the way to store the target vCPU in the rank
Date: Wed, 7 Oct 2015 20:13:34 +0100	[thread overview]
Message-ID: <56156EDE.8020209@citrix.com> (raw)
In-Reply-To: <56154878.6060506@citrix.com>

On 07/10/15 17:29, Julien Grall wrote:
> On 07/10/15 17:00, Ian Campbell wrote:
>> On Wed, 2015-10-07 at 16:48 +0100, Julien Grall wrote:
>>> On 07/10/15 16:38, Ian Campbell wrote:
>>>> On Wed, 2015-10-07 at 15:41 +0100, Julien Grall wrote:
>>>>> Note that with these changes, any read to those registers will list
>>>>> only
>>>>> the target vCPU used by Xen. We think this is likely to be OK because
>>>>> the
>>>>> GIC spec doesn't require to return exactly the value written and it
>>>>> can 
>>>>> be seen as if we decide to implement the register read-only.
>>>>
>>>> This still isn't true.
>>>
>>> I understood you previous answer on v2 as please replace "this is
>>> fine..." by "We think this is likely to be OK because..."....
>>
>> Sorry, I meant ... as "and go on to explain it as we've been discussing".
>>
>>>> The GIC spec requires one of two modes: Either the register is read
>>>> -only
>>>> _or_ it is writable and one can expect to read back what was written
>>>> (because the spec doesn't say otherwise and doing otherwise would
>>>> definitely be exceptional behaviour).
>>>
>>> How can you say that the spec requires the second mode? Nothing in the
>>> spec say that you can expect to read back what was written...
>>
>> Because that is so clearly and obviously the only sane default for a read
>> write register that nobody even bothers to say it. They specify when it is
>> not the case that you get back what you wrote by defining what you get on
>> read.
> 
> Well that's not obvious for me...
> 
>>> The spec only says what you the format of the register and what you may
>>> expect to read if the register is read-only. Other than that it's
>>> completely blur and you can implement whatever you want.
>>
>> Regardless, I am not acking in a patch which implies we think this
>> behaviour is justified by the spec as this one currently does.
> 
> TBH, I don't see how I can justify that what we are doing is fine except
> by saying "for simplicity".

I though a bit more about it. We are both interpreting the spec
differently and I think both are valid. So hardware people and OS
developer may also lean toward one of them.

Mine is more restrictive than yours, as you said on v1, it would hit
picky OS that follow your interpretation and read back the register to
check either the value is exactly the one written and/or the previous
value. Although it make the implementation simpler and save memory.

How about:

"Note that with these changes, any read to those registers will list
only the target vCPU used by Xen. As the spec is not clear whether this
is a valid choice or not, picky OSes (i.e which read back register to
check the value written) which have a different interpretation of the
spec may not boot anymore on Xen. Although, I think this is a fair trade
between memory usage in Xen (1KB on a domain using 4 vCPUs with no SPIs)
and a strict interpretation of the spec (though all the cases are not
clearly defined)".

Regards,

-- 
Julien Grall

  reply	other threads:[~2015-10-07 19:15 UTC|newest]

Thread overview: 34+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-10-07 14:41 [PATCH v3 0/9] xen/arm: vgic: Support 32-bit access for 64-bit register Julien Grall
2015-10-07 14:41 ` [PATCH v3 1/9] xen/arm: io: remove mmio_check_t typedef Julien Grall
2015-10-07 14:41 ` [PATCH v3 2/9] xen/arm: io: Extend write/read handler to pass the register in parameter Julien Grall
2015-10-07 14:41 ` [PATCH v3 3/9] xen/arm: io: Support sign-extension for every read access Julien Grall
2015-10-07 14:41 ` [PATCH v3 4/9] xen/arm: vgic: ctlr stores a 32-bit hardware register so use uint32_t Julien Grall
2015-10-07 14:41 ` [PATCH v3 5/9] xen/arm: vgic: Optimize the way to store GICD_IPRIORITYR in the rank Julien Grall
2015-10-07 14:41 ` [PATCH v3 6/9] xen/arm: vgic: Introduce a new field to store the rank index and use it Julien Grall
2015-10-07 14:41 ` [PATCH v3 7/9] xen/arm: vgic: Optimize the way to store the target vCPU in the rank Julien Grall
2015-10-07 15:38   ` Ian Campbell
2015-10-07 15:48     ` Julien Grall
2015-10-07 16:00       ` Ian Campbell
2015-10-07 16:29         ` Julien Grall
2015-10-07 19:13           ` Julien Grall [this message]
2015-10-08  9:39             ` Ian Campbell
2015-10-08 10:43               ` Julien Grall
2015-10-07 17:26   ` Stefano Stabellini
2015-10-07 18:16     ` Julien Grall
2015-10-08 10:56       ` Ian Campbell
2015-10-08 11:36         ` Stefano Stabellini
2015-10-08 12:23           ` Ian Campbell
2015-10-08 12:34             ` Stefano Stabellini
2015-10-08 13:46             ` Julien Grall
2015-10-08 14:25               ` Ian Campbell
2015-10-08 18:36                 ` Julien Grall
2015-10-09 11:24                   ` Julien Grall
2015-10-09 11:38                     ` Ian Campbell
2015-10-12 10:41                 ` Stefano Stabellini
2015-10-12 11:00                   ` Julien Grall
2015-10-12 11:07                     ` Stefano Stabellini
2015-10-12 11:28                       ` Julien Grall
2015-10-07 14:41 ` [PATCH v3 8/9] xen/arm: vgic: Introduce helpers to extract/update/clear/set vGIC register Julien Grall
2015-10-07 14:41 ` [PATCH v3 9/9] xen/arm: vgic-v3: Support 32-bit access for 64-bit registers Julien Grall
2015-10-08 10:44 ` [PATCH v3 0/9] xen/arm: vgic: Support 32-bit access for 64-bit register Julien Grall
2015-10-08 11:46   ` Ian Campbell

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