From mboxrd@z Thu Jan  1 00:00:00 1970
From: Julien Grall <julien.grall@citrix.com>
Subject: Re: [PATCH v3 7/9] xen/arm: vgic: Optimize the way to
 store the target vCPU in the rank
Date: Mon, 12 Oct 2015 12:00:59 +0100
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To: Stefano Stabellini <stefano.stabellini@eu.citrix.com>, Ian Campbell <ian.campbell@citrix.com>
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On 12/10/15 11:41, Stefano Stabellini wrote:
> On Thu, 8 Oct 2015, Ian Campbell wrote:
>>> If the concern is the behavior is changed, I'm happy to rework this code
>>> to keep exactly the same behavior. I.e any 32-bit write containing
>>> a 0 byte will be ignored. This is not optimal but at least I'm not
>>> opening the pandora box of fixing every single error in the code touch
>>> by this series.
>>
>> I'm okay with the new behaviour, I think Stefano was willing to tolerate it
>> (based on <alpine.DEB.2.02.1510081220190.1179@kaball.uk.xensource.com>).
>>
>> So if we aren't going to fix it to DTRT WRT writing zero to a target then I
>> think we can go with the current variant and not change to ignoring any
>> word with a zero byte in it.
>  
> OK.
> 
> BTW it would be interesting to see how real hardware behaves in this
> regard. I seem to recall that X-Gene was ignoring 0 writes too.

What do you mean by 0 writes? Is it the write ignored if one byte is 0?

Although, it's really depend if you try on a target register where all
the byte correspond to an implemented field or not.

Based on the spec (4.3.12 ARM IHI 0048B.b), a field corresponding to an
interrupt not implemented (i.e not wired) is RAZ/WI.

Regards,

-- 
Julien Grall