From mboxrd@z Thu Jan 1 00:00:00 1970 From: Julien Grall Subject: Re: [PATCH v3 7/9] xen/arm: vgic: Optimize the way to store the target vCPU in the rank Date: Mon, 12 Oct 2015 12:28:52 +0100 Message-ID: <561B9974.7060504@citrix.com> References: <1444228871-383-1-git-send-email-julien.grall@citrix.com> <1444228871-383-8-git-send-email-julien.grall@citrix.com> <56156161.4090109@citrix.com> <1444301795.1410.148.camel@citrix.com> <1444307021.1410.170.camel@citrix.com> <561673A8.8050608@citrix.com> <1444314312.1410.206.camel@citrix.com> <561B92EB.1020206@citrix.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mail6.bemta3.messagelabs.com ([195.245.230.39]) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1ZlbJ5-0005zC-5g for xen-devel@lists.xenproject.org; Mon, 12 Oct 2015 11:30:23 +0000 In-Reply-To: List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org To: Stefano Stabellini Cc: xen-devel@lists.xenproject.org, Ian Campbell List-Id: xen-devel@lists.xenproject.org On 12/10/15 12:07, Stefano Stabellini wrote: > On Mon, 12 Oct 2015, Julien Grall wrote: >> On 12/10/15 11:41, Stefano Stabellini wrote: >>> On Thu, 8 Oct 2015, Ian Campbell wrote: >>>>> If the concern is the behavior is changed, I'm happy to rework this code >>>>> to keep exactly the same behavior. I.e any 32-bit write containing >>>>> a 0 byte will be ignored. This is not optimal but at least I'm not >>>>> opening the pandora box of fixing every single error in the code touch >>>>> by this series. >>>> >>>> I'm okay with the new behaviour, I think Stefano was willing to tolerate it >>>> (based on ). >>>> >>>> So if we aren't going to fix it to DTRT WRT writing zero to a target then I >>>> think we can go with the current variant and not change to ignoring any >>>> word with a zero byte in it. >>> >>> OK. >>> >>> BTW it would be interesting to see how real hardware behaves in this >>> regard. I seem to recall that X-Gene was ignoring 0 writes too. >> >> What do you mean by 0 writes? Is it the write ignored if one byte is 0? > > Yes, for either 32bit or 8bit writes. I just gave a try on X-gene and any write is store even if it contains a 0 byte: (XEN) ITARGET56 = 0x1010101 (XEN) w 0x2020200 r 0x2020200 (XEN) w 0x4040004 r 0x4040004 (XEN) w 0x8000808 r 0x8000808 (XEN) w 0x101010 r 0x101010 diff --git a/xen/arch/arm/gic-v2.c b/xen/arch/arm/gic-v2.c index 5841e59..743c9eb 100644 --- a/xen/arch/arm/gic-v2.c +++ b/xen/arch/arm/gic-v2.c @@ -279,6 +279,32 @@ static void __init gicv2_dist_init(void) for ( i = 32; i < nr_lines; i += 4 ) writel_gicd(cpumask, GICD_ITARGETSR + (i / 4) * 4); + for ( i = 32; i < nr_lines; i += 4 ) + { + int n = i / 4; + int j = 0; + unsigned int reg = GICD_ITARGETSR + (i / 4) * 4; + + printk("ITARGET%u = 0x%x\n", n, readl_gicd(reg)); + + for ( j = 0; j < 4; j++ ) + { + uint32_t tmp = 1 << (j + 1); + + tmp |= tmp << 8; + tmp |= tmp << 16; + + /* Mask the field j */ + tmp &= ~((0xff) << (j * 8)); + + writel_gicd(tmp, reg); + + printk("\t w 0x%x r 0x%x\n", tmp, readl_gicd(reg)); + } + } + + while (1); + /* Default priority for global interrupts */ for ( i = 32; i < nr_lines; i += 4 ) writel_gicd(GIC_PRI_IRQ << 24 | GIC_PRI_IRQ << 16 | Regards, -- Julien Grall