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From: Julien Grall <julien.grall@citrix.com>
To: Stefano Stabellini <stefano.stabellini@eu.citrix.com>
Cc: xen-devel@lists.xenproject.org, ian.campbell@citrix.com
Subject: Re: [PATCH v5 3/6] xen/arm: vgic-v2: Don't ignore a write in ITARGETSR if one field is 0
Date: Fri, 13 Nov 2015 15:39:04 +0000	[thread overview]
Message-ID: <56460418.5060202@citrix.com> (raw)
In-Reply-To: <alpine.DEB.2.02.1511131504560.2653@kaball.uk.xensource.com>

On 13/11/15 15:05, Stefano Stabellini wrote:
> On Fri, 13 Nov 2015, Julien Grall wrote:
>> On 13/11/15 14:37, Stefano Stabellini wrote:
>>> On Mon, 9 Nov 2015, Julien Grall wrote:
>>>> +    for ( i = 0; i < NR_TARGETS_PER_ITARGETSR; i++, offset++, virq++ )
>>>
>>> offset is not needed in the loop
>>
>> offset is used in patch #4. Until v3, this patch was melted in patch #4
>> and by mistake I move the change here.
>>
>> So all the changes, the 3 lines above + this one, are valid after the
>> patch #4.
>>
>> Given that I don't expect much changes in this version, I won't bother
>> to rework it for this minor and harmless changes.
> 
> Each patch should stand on its own. What if a week from now we want to
> revert patch #4 because it causes regressions?

Well you will have a pointless variable incremented. But that's harmless.

However, you won't be able to easily revert patch #4 as the follow-up
patches relies on it.

TBH, I'm surprised that you are complaining about a meaningless change
while ugly (and unavoidable) code as been acked without a single remark
(see patch #2).

I'm not plan to resend the whole series for only this change. But feel
free to do it yourself.

Regards,

-- 
Julien Grall

  reply	other threads:[~2015-11-13 15:40 UTC|newest]

Thread overview: 19+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-11-09 15:49 [PATCH v5 0/6] xen/arm: vgic: Support 32-bit access for 64-bit register Julien Grall
2015-11-09 15:49 ` [PATCH v5 1/6] xen/arm: vgic-v2: Implement correctly ITARGETSR0 - ITARGETSR7 read-only Julien Grall
2015-11-13 11:18   ` Stefano Stabellini
2015-11-16 13:23   ` Ian Campbell
2015-11-18 16:20     ` Julien Grall
2015-11-09 15:49 ` [PATCH v5 2/6] xen/arm: vgic-v2: Handle correctly byte write in ITARGETSR Julien Grall
2015-11-13 12:08   ` Stefano Stabellini
2015-11-09 15:49 ` [PATCH v5 3/6] xen/arm: vgic-v2: Don't ignore a write in ITARGETSR if one field is 0 Julien Grall
2015-11-13 14:37   ` Stefano Stabellini
2015-11-13 14:52     ` Julien Grall
2015-11-13 15:05       ` Stefano Stabellini
2015-11-13 15:39         ` Julien Grall [this message]
2015-11-09 15:49 ` [PATCH v5 4/6] xen/arm: vgic: Optimize the way to store the target vCPU in the rank Julien Grall
2015-11-13 15:44   ` Stefano Stabellini
2015-11-13 15:49     ` Julien Grall
2015-11-09 15:49 ` [PATCH v5 5/6] xen/arm: vgic: Introduce helpers to extract/update/clear/set vGIC register Julien Grall
2015-11-11 16:09   ` Julien Grall
2015-11-16 13:14     ` Ian Campbell
2015-11-09 15:49 ` [PATCH v5 6/6] xen/arm: vgic-v3: Support 32-bit access for 64-bit registers Julien Grall

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