From: Boris Ostrovsky <boris.ostrovsky@oracle.com>
To: Andrew Cooper <andrew.cooper3@citrix.com>,
Jan Beulich <JBeulich@suse.com>
Cc: keir@xen.org, xen-devel@lists.xen.org
Subject: Re: [PATCH v2 0/2] Support of RO MMCFG access for PVH/HVMlite dom0s
Date: Fri, 18 Dec 2015 08:53:43 -0500 [thread overview]
Message-ID: <56740FE7.60301@oracle.com> (raw)
In-Reply-To: <567403D4.9070708@citrix.com>
On 12/18/2015 08:02 AM, Andrew Cooper wrote:
> On 18/12/15 10:11, Jan Beulich wrote:
>>>>> On 17.12.15 at 21:22, <boris.ostrovsky@oracle.com> wrote:
>>> * Left non-MMCFG RO accesses unhandled (we havent't encountered those accesses
>>> yet with PVH dom0 and it's probably better to fault on them and investigate
>>> whether they are guest's issues).
>> I seriously question this being a good approach,
> I concur. All accesses should be terminated somehow, even if this is
> the hypervisor dropping writes and completing reads with ~0's.
>
> This is the expected behaviour from the x86 architecture.
OK, I'll add that in.
To answer Jan's question, I did try 'vga=keep' and that worked fine. (I
couldn't test AMD IOMMU because we don't support PVH there and I don't
have the other HW that he mentioned).
-boris
next prev parent reply other threads:[~2015-12-18 13:53 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-12-17 20:22 [PATCH v2 0/2] Support of RO MMCFG access for PVH/HVMlite dom0s Boris Ostrovsky
2015-12-17 20:22 ` [PATCH v2 1/2] x86/mm: Add information about faulted page's presence to npfec structure Boris Ostrovsky
2015-12-18 10:15 ` Jan Beulich
2015-12-20 6:49 ` Tian, Kevin
2015-12-17 20:22 ` [PATCH v2 2/2] x86/PCI: Intercept Dom0 MMCFG from dom0s in HVM containers Boris Ostrovsky
2015-12-18 10:28 ` Jan Beulich
2015-12-18 10:11 ` [PATCH v2 0/2] Support of RO MMCFG access for PVH/HVMlite dom0s Jan Beulich
2015-12-18 13:02 ` Andrew Cooper
2015-12-18 13:53 ` Boris Ostrovsky [this message]
2015-12-18 14:16 ` Jan Beulich
2015-12-18 14:30 ` Boris Ostrovsky
2015-12-18 14:36 ` Jan Beulich
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