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From: =?UTF-8?Q?Roger_Pau_Monn=c3=a9?= <roger.pau@citrix.com>
Subject: Re: HVMlite ABI specification DRAFT A
Date: Fri, 5 Feb 2016 12:50:45 +0100
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To: Jan Beulich <JBeulich@suse.com>
Cc: Wei Liu <wei.liu2@citrix.com>, Stefano Stabellini <stefano.stabellini@eu.citrix.com>, Andrew Cooper <andrew.cooper3@citrix.com>, Tim Deegan <tim@xen.org>, Paul Durrant <paul.durrant@citrix.com>, David Vrabel <david.vrabel@citrix.com>, xen-devel <xen-devel@lists.xenproject.org>, samuel.thibault@ens-lyon.org, Boris Ostrovsky <boris.ostrovsky@oracle.com>
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El 5/2/16 a les 12:45, Jan Beulich ha escrit:
>>>> On 05.02.16 at 12:30, <roger.pau@citrix.com> wrote:
>> El 5/2/16 a les 11:40, Jan Beulich ha escrit:
>>>>>> On 05.02.16 at 10:50, <roger.pau@citrix.com> wrote:
>>>> For legacy PCI interrupts, we can parse the MADT inside of Xen in order
>>>> to properly setup the lines/overwrites and inject the interrupts that
>>>> are not handled by Xen straight into the hardware domain. This will
>>>> require us to be able to emulate the same topology as what is found in
>>>> native (eg: if there are two IO APICs in the hardware we should also
>>>> provide two emulated ones to the hw domain).
>>>
>>> I don't think MADT contains all the needed information, or else we
>>> wouldn't need PHYSDEVOP_setup_gsi.
>>
>> AFAICT, I think we could do something like:
>>
>>  - IRQs [0, 15]: edge-trigger, low-polarity.
>>  - IRQs [16, n]: level-triggered, high-polarity.
> 
> That's not a valid assumption - I've seen systems with other settings
> on GSI >= 16 ...

Then we just propagate how the emulated IO APIC pins are setup to the
real one, this should match reality, and is no different from using
PHYSDEVOP_setup_gsi. AFAICT it's just a different way of getting the
same information.

Roger.