* [PATCH v2] x86emul: relax asm() constraints
@ 2016-02-16 10:16 Jan Beulich
2016-02-16 11:14 ` Andrew Cooper
0 siblings, 1 reply; 2+ messages in thread
From: Jan Beulich @ 2016-02-16 10:16 UTC (permalink / raw)
To: xen-devel; +Cc: Andrew Cooper, Keir Fraser
[-- Attachment #1: Type: text/plain, Size: 3355 bytes --]
Let's give the compiler as much liberty at picking instruction operands
as possible. Also drop unnecessary size modifiers when the correct size
can already be derived from the asm() operands. Finally also drop an
"unsigned" from idiv_dbl()'s second parameter, allowing a cast to be
eliminated.
Signed-off-by: Jan Beulich <jbeulich@suse.com>
---
v2: Extend a couple of "=q" to "=qm" and one (in div_dbl()) "r" to "rm".
--- a/xen/arch/x86/x86_emulate/x86_emulate.c
+++ b/xen/arch/x86/x86_emulate/x86_emulate.c
@@ -611,7 +611,7 @@ do {
*/
static bool_t even_parity(uint8_t v)
{
- asm ( "test %b0,%b0; setp %b0" : "=a" (v) : "0" (v) );
+ asm ( "test %1,%1; setp %0" : "=qm" (v) : "q" (v) );
return v;
}
@@ -813,9 +813,9 @@ static int read_ulong(
*/
static bool_t mul_dbl(unsigned long m[2])
{
- bool_t rc = 0;
- asm ( "mul %1; seto %b2"
- : "+a" (m[0]), "+d" (m[1]), "+q" (rc) );
+ bool_t rc;
+ asm ( "mul %1; seto %2"
+ : "+a" (m[0]), "+d" (m[1]), "=qm" (rc) );
return rc;
}
@@ -826,9 +826,9 @@ static bool_t mul_dbl(unsigned long m[2]
*/
static bool_t imul_dbl(unsigned long m[2])
{
- bool_t rc = 0;
- asm ( "imul %1; seto %b2"
- : "+a" (m[0]), "+d" (m[1]), "+q" (rc) );
+ bool_t rc;
+ asm ( "imul %1; seto %2"
+ : "+a" (m[0]), "+d" (m[1]), "=qm" (rc) );
return rc;
}
@@ -842,7 +842,7 @@ static bool_t div_dbl(unsigned long u[2]
{
if ( (v == 0) || (u[1] >= v) )
return 1;
- asm ( "div %2" : "+a" (u[0]), "+d" (u[1]) : "r" (v) );
+ asm ( "divq %2" : "+a" (u[0]), "+d" (u[1]) : "rm" (v) );
return 0;
}
@@ -854,9 +854,9 @@ static bool_t div_dbl(unsigned long u[2]
* NB. We don't use idiv directly as it's moderately hard to work out
* ahead of time whether it will #DE, which we cannot allow to happen.
*/
-static bool_t idiv_dbl(unsigned long u[2], unsigned long v)
+static bool_t idiv_dbl(unsigned long u[2], long v)
{
- bool_t negu = (long)u[1] < 0, negv = (long)v < 0;
+ bool_t negu = (long)u[1] < 0, negv = v < 0;
/* u = abs(u) */
if ( negu )
@@ -4542,9 +4542,10 @@ x86_emulate(
case 0xbc: /* bsf or tzcnt */ {
bool_t zf;
- asm ( "bsf %2,%0; setz %b1"
- : "=r" (dst.val), "=q" (zf)
- : "r" (src.val) );
+
+ asm ( "bsf %2,%0; setz %1"
+ : "=r" (dst.val), "=qm" (zf)
+ : "rm" (src.val) );
_regs.eflags &= ~EFLG_ZF;
if ( (vex.pfx == vex_f3) && vcpu_has_bmi1() )
{
@@ -4567,9 +4568,10 @@ x86_emulate(
case 0xbd: /* bsr or lzcnt */ {
bool_t zf;
- asm ( "bsr %2,%0; setz %b1"
- : "=r" (dst.val), "=q" (zf)
- : "r" (src.val) );
+
+ asm ( "bsr %2,%0; setz %1"
+ : "=r" (dst.val), "=qm" (zf)
+ : "rm" (src.val) );
_regs.eflags &= ~EFLG_ZF;
if ( (vex.pfx == vex_f3) && vcpu_has_lzcnt() )
{
@@ -4698,7 +4700,7 @@ x86_emulate(
break;
case 4:
#ifdef __x86_64__
- asm ( "bswap %k0" : "=r" (dst.val) : "0" (*dst.reg) );
+ asm ( "bswap %k0" : "=r" (dst.val) : "0" (*(uint32_t *)dst.reg) );
break;
case 8:
#endif
[-- Attachment #2: x86emul-asm-constraint.patch --]
[-- Type: text/plain, Size: 3385 bytes --]
x86emul: relax asm() constraints
Let's give the compiler as much liberty at picking instruction operands
as possible. Also drop unnecessary size modifiers when the correct size
can already be derived from the asm() operands. Finally also drop an
"unsigned" from idiv_dbl()'s second parameter, allowing a cast to be
eliminated.
Signed-off-by: Jan Beulich <jbeulich@suse.com>
---
v2: Extend a couple of "=q" to "=qm" and one (in div_dbl()) "r" to "rm".
--- a/xen/arch/x86/x86_emulate/x86_emulate.c
+++ b/xen/arch/x86/x86_emulate/x86_emulate.c
@@ -611,7 +611,7 @@ do {
*/
static bool_t even_parity(uint8_t v)
{
- asm ( "test %b0,%b0; setp %b0" : "=a" (v) : "0" (v) );
+ asm ( "test %1,%1; setp %0" : "=qm" (v) : "q" (v) );
return v;
}
@@ -813,9 +813,9 @@ static int read_ulong(
*/
static bool_t mul_dbl(unsigned long m[2])
{
- bool_t rc = 0;
- asm ( "mul %1; seto %b2"
- : "+a" (m[0]), "+d" (m[1]), "+q" (rc) );
+ bool_t rc;
+ asm ( "mul %1; seto %2"
+ : "+a" (m[0]), "+d" (m[1]), "=qm" (rc) );
return rc;
}
@@ -826,9 +826,9 @@ static bool_t mul_dbl(unsigned long m[2]
*/
static bool_t imul_dbl(unsigned long m[2])
{
- bool_t rc = 0;
- asm ( "imul %1; seto %b2"
- : "+a" (m[0]), "+d" (m[1]), "+q" (rc) );
+ bool_t rc;
+ asm ( "imul %1; seto %2"
+ : "+a" (m[0]), "+d" (m[1]), "=qm" (rc) );
return rc;
}
@@ -842,7 +842,7 @@ static bool_t div_dbl(unsigned long u[2]
{
if ( (v == 0) || (u[1] >= v) )
return 1;
- asm ( "div %2" : "+a" (u[0]), "+d" (u[1]) : "r" (v) );
+ asm ( "divq %2" : "+a" (u[0]), "+d" (u[1]) : "rm" (v) );
return 0;
}
@@ -854,9 +854,9 @@ static bool_t div_dbl(unsigned long u[2]
* NB. We don't use idiv directly as it's moderately hard to work out
* ahead of time whether it will #DE, which we cannot allow to happen.
*/
-static bool_t idiv_dbl(unsigned long u[2], unsigned long v)
+static bool_t idiv_dbl(unsigned long u[2], long v)
{
- bool_t negu = (long)u[1] < 0, negv = (long)v < 0;
+ bool_t negu = (long)u[1] < 0, negv = v < 0;
/* u = abs(u) */
if ( negu )
@@ -4542,9 +4542,10 @@ x86_emulate(
case 0xbc: /* bsf or tzcnt */ {
bool_t zf;
- asm ( "bsf %2,%0; setz %b1"
- : "=r" (dst.val), "=q" (zf)
- : "r" (src.val) );
+
+ asm ( "bsf %2,%0; setz %1"
+ : "=r" (dst.val), "=qm" (zf)
+ : "rm" (src.val) );
_regs.eflags &= ~EFLG_ZF;
if ( (vex.pfx == vex_f3) && vcpu_has_bmi1() )
{
@@ -4567,9 +4568,10 @@ x86_emulate(
case 0xbd: /* bsr or lzcnt */ {
bool_t zf;
- asm ( "bsr %2,%0; setz %b1"
- : "=r" (dst.val), "=q" (zf)
- : "r" (src.val) );
+
+ asm ( "bsr %2,%0; setz %1"
+ : "=r" (dst.val), "=qm" (zf)
+ : "rm" (src.val) );
_regs.eflags &= ~EFLG_ZF;
if ( (vex.pfx == vex_f3) && vcpu_has_lzcnt() )
{
@@ -4698,7 +4700,7 @@ x86_emulate(
break;
case 4:
#ifdef __x86_64__
- asm ( "bswap %k0" : "=r" (dst.val) : "0" (*dst.reg) );
+ asm ( "bswap %k0" : "=r" (dst.val) : "0" (*(uint32_t *)dst.reg) );
break;
case 8:
#endif
[-- Attachment #3: Type: text/plain, Size: 126 bytes --]
_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xen.org
http://lists.xen.org/xen-devel
^ permalink raw reply [flat|nested] 2+ messages in thread
* Re: [PATCH v2] x86emul: relax asm() constraints
2016-02-16 10:16 [PATCH v2] x86emul: relax asm() constraints Jan Beulich
@ 2016-02-16 11:14 ` Andrew Cooper
0 siblings, 0 replies; 2+ messages in thread
From: Andrew Cooper @ 2016-02-16 11:14 UTC (permalink / raw)
To: Jan Beulich, xen-devel; +Cc: Keir Fraser
On 16/02/16 10:16, Jan Beulich wrote:
> Let's give the compiler as much liberty at picking instruction operands
> as possible. Also drop unnecessary size modifiers when the correct size
> can already be derived from the asm() operands. Finally also drop an
> "unsigned" from idiv_dbl()'s second parameter, allowing a cast to be
> eliminated.
>
> Signed-off-by: Jan Beulich <jbeulich@suse.com>
Reviewed-by: Andrew Cooper <andrew.cooper3@citrix.com>
^ permalink raw reply [flat|nested] 2+ messages in thread
end of thread, other threads:[~2016-02-16 11:14 UTC | newest]
Thread overview: 2+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2016-02-16 10:16 [PATCH v2] x86emul: relax asm() constraints Jan Beulich
2016-02-16 11:14 ` Andrew Cooper
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).