From mboxrd@z Thu Jan  1 00:00:00 1970
From: Andrew Cooper <andrew.cooper3@citrix.com>
Subject: Re: [PATCH v2.5 31/30] Fix PV guest XSAVE handling with
	levelling
Date: Wed, 17 Feb 2016 13:06:36 +0000
Message-ID: <56C4705C.6020003@citrix.com>
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To: Jan Beulich <JBeulich@suse.com>
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On 17/02/16 09:02, Jan Beulich wrote:
>>>> On 08.02.16 at 18:26, <andrew.cooper3@citrix.com> wrote:
> This fiddles with behavior on AMD only, yet it's not obvious why this
> couldn't be done in vendor independent code (it should, afaict, be
> benign for Intel).

AMD and Intel levelling are fundamentally different.

The former are override MSRs with some quirks when it comes to the magic
bits, while the latter are strict masks which take effect before the
magic bits are folded in.

~Andrew