From: Andrew Cooper <andrew.cooper3@citrix.com>
To: Jan Beulich <JBeulich@suse.com>,
xen-devel <xen-devel@lists.xenproject.org>
Subject: Re: [PATCH v4 04/17] x86emul: support {, V}{, U}COMIS{S, D}
Date: Wed, 1 Mar 2017 14:16:59 +0000 [thread overview]
Message-ID: <56a3b75a-6e68-54c8-a50d-b515dadd8c42@citrix.com> (raw)
In-Reply-To: <58B58068020000780013E2A8@prv-mh.provo.novell.com>
On 28/02/17 12:51, Jan Beulich wrote:
> Signed-off-by: Jan Beulich <jbeulich@suse.com>
> ---
> v4: Add missing copy_REX_VEX().
> v3: Ignore VEX.l. Add fic.exn_raised constraint to invoke_stub() use.
> v2: Add missing RET to stub. Generate #UD (instead of simply failing)
> when VEX.l is disallowed.
>
> --- a/xen/arch/x86/x86_emulate/x86_emulate.c
> +++ b/xen/arch/x86/x86_emulate/x86_emulate.c
> @@ -254,7 +254,7 @@ static const struct {
> [0x2a] = { DstImplicit|SrcMem|ModRM|Mov, simd_other },
> [0x2b] = { DstMem|SrcImplicit|ModRM|Mov, simd_any_fp },
> [0x2c ... 0x2d] = { DstImplicit|SrcMem|ModRM|Mov, simd_other },
> - [0x2e ... 0x2f] = { ImplicitOps|ModRM },
> + [0x2e ... 0x2f] = { ImplicitOps|ModRM|TwoOp },
> [0x30 ... 0x35] = { ImplicitOps },
> [0x37] = { ImplicitOps },
> [0x38] = { DstReg|SrcMem|ModRM },
> @@ -5468,6 +5468,55 @@ x86_emulate(
> state->simd_size = simd_none;
> break;
>
> + CASE_SIMD_PACKED_FP(, 0x0f, 0x2e): /* ucomis{s,d} xmm/mem,xmm */
> + CASE_SIMD_PACKED_FP(_VEX, 0x0f, 0x2e): /* vucomis{s,d} xmm/mem,xmm */
> + CASE_SIMD_PACKED_FP(, 0x0f, 0x2f): /* comis{s,d} xmm/mem,xmm */
> + CASE_SIMD_PACKED_FP(_VEX, 0x0f, 0x2f): /* vcomis{s,d} xmm/mem,xmm */
> + if ( vex.opcx == vex_none )
> + {
> + if ( vex.pfx )
> + vcpu_must_have(sse2);
> + else
> + vcpu_must_have(sse);
> + get_fpu(X86EMUL_FPU_xmm, &fic);
> + }
> + else
> + {
> + host_and_vcpu_must_have(avx);
> + get_fpu(X86EMUL_FPU_ymm, &fic);
> + }
This is starting to become a common sequence. Is there any sensible way
to factor it out in a non-macro way, to avoid the compiler instantiating
it at the top of many basic blocks?
> +
> + opc = init_prefixes(stub);
> + opc[0] = b;
> + opc[1] = modrm;
> + if ( ea.type == OP_MEM )
> + {
> + rc = ops->read(ea.mem.seg, ea.mem.off, mmvalp, vex.pfx ? 8 : 4,
> + ctxt);
> + if ( rc != X86EMUL_OKAY )
> + goto done;
> +
> + /* Convert memory operand to (%rAX). */
> + rex_prefix &= ~REX_B;
> + vex.b = 1;
> + opc[1] &= 0x38;
> + }
> + fic.insn_bytes = PFX_BYTES + 2;
> + opc[2] = 0xc3;
> +
> + copy_REX_VEX(opc, rex_prefix, vex);
> + invoke_stub(_PRE_EFLAGS("[eflags]", "[mask]", "[tmp]"),
> + _POST_EFLAGS("[eflags]", "[mask]", "[tmp]"),
> + [eflags] "+g" (_regs._eflags),
> + [tmp] "=&r" (cr4 /* dummy */), "+m" (*mmvalp),
This is latently dangerous. It would be better to have an explicit
"unsigned long dummy;", which the compiler will perfectly easily elide
during register scheduling.
~Andrew
> + "+m" (fic.exn_raised)
> + : [func] "rm" (stub.func), "a" (mmvalp),
> + [mask] "i" (EFLAGS_MASK));
> +
> + put_stub(stub);
> + put_fpu(&fic);
> + break;
> +
> case X86EMUL_OPC(0x0f, 0x30): /* wrmsr */
> generate_exception_if(!mode_ring0(), EXC_GP, 0);
> fail_if(ops->write_msr == NULL);
>
>
>
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next prev parent reply other threads:[~2017-03-01 14:17 UTC|newest]
Thread overview: 46+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-02-28 12:42 [PATCH v4 00/17] x86emul: MMX/SSEn support Jan Beulich
2017-02-28 12:49 ` [PATCH v4 01/17] x86emul: support most memory accessing MMX/SSE{, 2, 3} insns Jan Beulich
2017-03-01 13:17 ` Andrew Cooper
2017-03-01 13:50 ` Jan Beulich
2017-03-01 18:08 ` Andrew Cooper
2017-02-28 12:50 ` [PATCH v4 02/17] x86emul: support MMX/SSE{,2,3} moves Jan Beulich
2017-03-01 13:59 ` [PATCH v4 02/17] x86emul: support MMX/SSE{, 2, 3} moves Andrew Cooper
2017-03-01 14:19 ` Jan Beulich
2017-03-01 19:56 ` Andrew Cooper
2017-03-02 8:07 ` Jan Beulich
2017-02-28 12:51 ` [PATCH v4 03/17] x86emul: support MMX/SSE/SSE2 converts Jan Beulich
2017-03-01 14:09 ` Andrew Cooper
2017-02-28 12:51 ` [PATCH v4 04/17] x86emul: support {,V}{,U}COMIS{S,D} Jan Beulich
2017-03-01 14:16 ` Andrew Cooper [this message]
2017-03-01 14:26 ` [PATCH v4 04/17] x86emul: support {, V}{, U}COMIS{S, D} Jan Beulich
2017-03-01 14:31 ` Andrew Cooper
2017-02-28 12:52 ` [PATCH v4 05/17] x86emul: support MMX/SSE{, 2, 4a} insns with only register operands Jan Beulich
2017-03-01 14:36 ` Andrew Cooper
2017-03-01 14:43 ` Jan Beulich
2017-03-01 20:01 ` Andrew Cooper
2017-02-28 12:52 ` [PATCH v4 06/17] x86emul: support {,V}{LD,ST}MXCSR Jan Beulich
2017-03-01 14:57 ` Andrew Cooper
2017-02-28 12:53 ` [PATCH v4 07/17] x86emul: support {,V}MOVNTDQA Jan Beulich
2017-03-01 14:58 ` Andrew Cooper
2017-02-28 12:53 ` [PATCH v4 08/17] x86emul: test coverage for SSE/SSE2 insns Jan Beulich
2017-02-28 12:54 ` [PATCH v4 09/17] x86emul: honor MMXEXT feature flag Jan Beulich
2017-02-28 12:54 ` [PATCH v4 10/17] x86emul: add tables for 0f38 and 0f3a extension space Jan Beulich
2017-03-01 15:49 ` Andrew Cooper
2017-03-01 16:11 ` Jan Beulich
2017-03-01 20:35 ` Andrew Cooper
2017-03-02 8:15 ` Jan Beulich
2017-02-28 12:55 ` [PATCH v4 11/17] x86emul: support SSSE3 insns Jan Beulich
2017-03-01 16:06 ` Andrew Cooper
2017-02-28 12:56 ` [PATCH v4 12/17] x86emul: support SSE4.1 insns Jan Beulich
2017-03-01 16:58 ` Andrew Cooper
2017-03-02 8:26 ` Jan Beulich
2017-02-28 12:56 ` [PATCH v4 13/17] x86emul: support SSE4.2 insns Jan Beulich
2017-03-01 17:21 ` Andrew Cooper
2017-02-28 12:57 ` [PATCH v4 14/17] x86emul: test coverage for SSE3/SSSE3/SSE4* insns Jan Beulich
2017-03-01 17:22 ` Andrew Cooper
2017-02-28 12:58 ` [PATCH v4 15/17] x86emul: support PCLMULQDQ Jan Beulich
2017-03-01 17:44 ` Andrew Cooper
2017-03-02 8:30 ` Jan Beulich
2017-02-28 12:58 ` [PATCH v4 16/17] x86emul: support AESNI insns Jan Beulich
2017-02-28 12:59 ` [PATCH v4 17/17] x86emul: support SHA insns Jan Beulich
2017-03-01 17:51 ` Andrew Cooper
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