xen-devel.lists.xenproject.org archive mirror
 help / color / mirror / Atom feed
* [PATCH] x86/MSI: handle both MSI-X and MSI in cfg space write intercept
@ 2016-04-21 15:45 Jan Beulich
  2016-04-22 17:20 ` Andrew Cooper
  2016-04-25 11:29 ` Wei Liu
  0 siblings, 2 replies; 3+ messages in thread
From: Jan Beulich @ 2016-04-21 15:45 UTC (permalink / raw)
  To: xen-devel; +Cc: Andrew Cooper, Keir Fraser, Wei Liu

[-- Attachment #1: Type: text/plain, Size: 1404 bytes --]

In commit aa7c1fdf9d ("x86/MSI: properly track guest masking requests")
I neglected to consider devices allowing for both MSI and MSI-X to be
used (not at the same time of course): The MSI-X part of the intercept
logic needs to fall through to the MSI one when the access is outside
the MSI-X capability bounds.

Signed-off-by: Jan Beulich <jbeulich@suse.com>

--- a/xen/arch/x86/msi.c
+++ b/xen/arch/x86/msi.c
@@ -1292,17 +1292,17 @@ int pci_msi_conf_write_intercept(struct
                                           PCI_CAP_ID_MSIX);
         ASSERT(pos);
 
-        if ( reg < pos || reg >= msix_pba_offset_reg(pos) + 4 )
-            return 0;
+        if ( reg >= pos && reg < msix_pba_offset_reg(pos) + 4 )
+        {
+            if ( reg != msix_control_reg(pos) || size != 2 )
+                return -EACCES;
 
-        if ( reg != msix_control_reg(pos) || size != 2 )
-            return -EACCES;
+            pdev->msix->guest_maskall = !!(*data & PCI_MSIX_FLAGS_MASKALL);
+            if ( pdev->msix->host_maskall )
+                *data |= PCI_MSIX_FLAGS_MASKALL;
 
-        pdev->msix->guest_maskall = !!(*data & PCI_MSIX_FLAGS_MASKALL);
-        if ( pdev->msix->host_maskall )
-            *data |= PCI_MSIX_FLAGS_MASKALL;
-
-        return 1;
+            return 1;
+        }
     }
 
     entry = find_msi_entry(pdev, -1, PCI_CAP_ID_MSI);




[-- Attachment #2: x86-MSI-intercept-both.patch --]
[-- Type: text/plain, Size: 1465 bytes --]

x86/MSI: handle both MSI-X and MSI in cfg space write intercept

In commit aa7c1fdf9d ("x86/MSI: properly track guest masking requests")
I neglected to consider devices allowing for both MSI and MSI-X to be
used (not at the same time of course): The MSI-X part of the intercept
logic needs to fall through to the MSI one when the access is outside
the MSI-X capability bounds.

Signed-off-by: Jan Beulich <jbeulich@suse.com>

--- a/xen/arch/x86/msi.c
+++ b/xen/arch/x86/msi.c
@@ -1292,17 +1292,17 @@ int pci_msi_conf_write_intercept(struct
                                           PCI_CAP_ID_MSIX);
         ASSERT(pos);
 
-        if ( reg < pos || reg >= msix_pba_offset_reg(pos) + 4 )
-            return 0;
+        if ( reg >= pos && reg < msix_pba_offset_reg(pos) + 4 )
+        {
+            if ( reg != msix_control_reg(pos) || size != 2 )
+                return -EACCES;
 
-        if ( reg != msix_control_reg(pos) || size != 2 )
-            return -EACCES;
+            pdev->msix->guest_maskall = !!(*data & PCI_MSIX_FLAGS_MASKALL);
+            if ( pdev->msix->host_maskall )
+                *data |= PCI_MSIX_FLAGS_MASKALL;
 
-        pdev->msix->guest_maskall = !!(*data & PCI_MSIX_FLAGS_MASKALL);
-        if ( pdev->msix->host_maskall )
-            *data |= PCI_MSIX_FLAGS_MASKALL;
-
-        return 1;
+            return 1;
+        }
     }
 
     entry = find_msi_entry(pdev, -1, PCI_CAP_ID_MSI);

[-- Attachment #3: Type: text/plain, Size: 126 bytes --]

_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xen.org
http://lists.xen.org/xen-devel

^ permalink raw reply	[flat|nested] 3+ messages in thread

end of thread, other threads:[~2016-04-25 11:27 UTC | newest]

Thread overview: 3+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2016-04-21 15:45 [PATCH] x86/MSI: handle both MSI-X and MSI in cfg space write intercept Jan Beulich
2016-04-22 17:20 ` Andrew Cooper
2016-04-25 11:29 ` Wei Liu

This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).