From: Julien Grall <julien.grall@arm.com>
To: Wei Chen <wei.chen@linaro.org>, xen-devel@lists.xen.org
Cc: sstabellini@kernel.org, steve.capper@arm.com
Subject: Re: [PATCH v2 3/4] xen:arm: arm64: Add correct MPIDR_HWID_MASK value for ARM64
Date: Fri, 27 May 2016 11:50:25 +0100 [thread overview]
Message-ID: <57482671.1090908@arm.com> (raw)
In-Reply-To: <20160526075843.25236-4-Wei.Chen@linaro.org>
Hi Wei,
On 26/05/16 08:58, Wei Chen wrote:
> Currently, MPIDR_HWID_MASK is using the bit definition of AArch32 MPIDR.
> From ARMv8 ARM we can see there are 4 levels of affinity on AArch64
> whilst AArch32 has only 3. So, this value is not correct when Xen is
> running on AArch64.
>
> Now, we use the value 0xff00ffffff for this macro on AArch64. But neither
> of this value and its bitwise invert value can be used in mov instruction
> with the encoding of {imm16:shift} or {imms:immr}. So we have to use ldr
> to load the bitwise invert value to register.
>
> The details of mov immediate encoding are listed in ARMv8 ARM C4.2.5.
The section numbering may change between two versions of the spec. I
would mention the version (e.g DDI 0487A.i, I guess?).
Regards,
--
Julien Grall
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next prev parent reply other threads:[~2016-05-27 10:50 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-05-26 7:58 [PATCH v2 0/4] xen/arm: arm64: Widen register access to mpidr to 64-bits Wei Chen
2016-05-26 7:58 ` [PATCH v2 1/4] xen/arm: Change the variable type of cpu_logical_map to register_t Wei Chen
2016-05-26 7:58 ` [PATCH v2 2/4] xen/arm: Make AFFINITY_MASK generate correct mask for level3 Wei Chen
2016-05-26 7:58 ` [PATCH v2 3/4] xen:arm: arm64: Add correct MPIDR_HWID_MASK value for ARM64 Wei Chen
2016-05-27 10:50 ` Julien Grall [this message]
2016-05-30 1:50 ` Wei Chen
2016-05-26 7:58 ` [PATCH v2 4/4] xen/arm: arm64: Remove MPIDR multiprocessing extensions check Wei Chen
2016-05-27 10:51 ` Julien Grall
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