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From: James Morse <james.morse@arm.com>
To: Julien Grall <julien.grall@arm.com>,
	Florian Jakobsmeier <florian.jakobsmeier@googlemail.com>
Cc: xen-devel <xen-devel@lists.xenproject.org>,
	Stefano Stabellini <sstabellini@kernel.org>
Subject: Re: xen/arm: Software Step ARMv8 - PC stuck on instruction
Date: Thu, 03 Aug 2017 10:49:06 +0100	[thread overview]
Message-ID: <5982F192.7050901@arm.com> (raw)
In-Reply-To: <51641005-94fc-2b04-ae49-25e84f3cc56f@arm.com>

Hi Florian, Julien,

On 02/08/17 14:32, Julien Grall wrote:
> On 26/07/17 14:12, Florian Jakobsmeier wrote:
>> i was just testing the single step implementation and realized that the
>> before mentioned solution is not fully working. I'm still trying to
>> enable SS for a VM on Xen.

>> To test my implementation i wrote a small Kernel Module and started it
>> in the DomU. The module only contains a loop which increments a counter
>> and prints its value.
>> Right after loading the moduleI start the single step mechanism in the
>> Dom0 for the VM (again with xen-access).
>> As soon as i start the SS the VM will stop working.

>> The ARM ARM (D2-1956 - ARM DDI 0487B.a ID033117) states that, in order
>> to enables software step:
>>
>>     A debugger enables MDSCR_EL1.SS = 1
>>
>>     Executes an ERET

...with SPSR.SS = 1, and you need to ERET with PSTATE.D disabled (which I assume
Xen always has).

This then becomes the guest's PSTATE.SS bit, which suppresses the single-step
exception until it has stepped one instruction.


>>     The PE executes the instruction to be single-stepped
>>
>>     Takes a software step exception on the next instruction


>> My guess is that by setting the needed SS registers ever time when we
>> leave the guest, the configuration won't allow the guest to execute the
>> "to be single stepped instruction"
>> Before executing the (first) instruction the VM will generate the SS
>> exception (as desired). In the hypervisor we will set the SS registers
>> again, which could hinder the VM to execute the instruction (which we
>> want because we already generated an SS exception for this instruction)
>> and instead generate a second SS exception for it. This will lead to the
>> second PC print in the single step handler

>> But I'm not able to find any proof for this.

I'm afraid the ARM-ARM could be clearer about how this works. (It's had me
confused all week!).

The state machine in figure D2-4 (D2.12.3 the software step state machine)
should help. I haven't looked at Xen (or your patch), but from your description
it sounds like you are entering the guest with the debug state machine in
active-pending state, then taking a single-step exception immediately. You never
actually execute the instruction-to-be-stepped.

Instead you want to enter the guest in active-not-pending state, the rules for
this are in 'D2.12.4 Entering the active-not-pending state'.


Thanks,

James

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  reply	other threads:[~2017-08-03  9:50 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-07-04 12:30 xen/arm: Software Step ARMv8 - PC stuck on instruction Florian Jakobsmeier
2017-07-04 18:37 ` Julien Grall
2017-07-05 14:03   ` Florian Jakobsmeier
2017-07-26 13:12     ` Florian Jakobsmeier
2017-08-02 13:32       ` Julien Grall
2017-08-03  9:49         ` James Morse [this message]
2017-08-03 10:16         ` Florian Jakobsmeier
2017-08-03 10:46           ` James Morse
2017-08-03 11:08             ` Julien Grall
2017-08-03 12:29               ` Florian Jakobsmeier
2017-08-03 13:02                 ` James Morse
2017-08-03 16:00                   ` Florian Jakobsmeier
2017-08-07 17:05                     ` James Morse

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