From mboxrd@z Thu Jan  1 00:00:00 1970
From: Justin Acker <ackerj67@yahoo.com>
Subject: xhci_hcd intterrupt affinity in Dom0/DomU limited to
 single interrupt
Date: Tue, 1 Sep 2015 17:39:46 +0000 (UTC)
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Taking this to the dev list from users.=20

Is there a way to force or enable pirq delivery to a set of cpus as opposed=
 to single device from being a assigned a single pirq so that its interrupt=
 can be distributed across multiple cpus? I believe the device drivers do s=
upport multiple queues when run natively without the Dom0 loaded. The devic=
e in question is the xhci_hcd driver for which I/O transfers seem to be slo=
wed when the Dom0 is loaded. The behavior seems to pass through to the DomU=
 if pass through is enabled. I found some similar threads, but most relate =
to Ethernet controllers. I tried some of the x2apic and x2apic_phys dom0 ke=
rnel arguments, but none distributed the pirqs. Based on the reading relati=
ng to IRQs for Xen, I think pinning the pirqs to cpu0 is done to avoid an i=
nterrupt storm. I tried IRQ balance and when configured/adjusted it will ba=
lance individual pirqs, but not multiple interrupts.



With irqbalance enabled in Dom0:

=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 CPU0=C2=A0=C2=
=A0=C2=A0=C2=A0=C2=A0=C2=A0 CPU1=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 CPU2=
=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 CPU3=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=
=A0 CPU4=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 CPU5=C2=A0=C2=A0=C2=A0=C2=A0=
=C2=A0=C2=A0 CPU6=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 CPU7=C2=A0=C2=A0=C2=
=A0=C2=A0=C2=A0=20
=C2=A076:=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 11304=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=
=C2=A0=C2=A0=C2=A0=C2=A0 0=C2=A0=C2=A0=C2=A0=C2=A0 149579=C2=A0=C2=A0=C2=A0=
=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=
=C2=A0=C2=A0=C2=A0 0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 =
0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 0=C2=A0=C2=A0=C2=A0=
=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 0=C2=A0 xen-pirq-msi=C2=A0=C2=A0=C2=A0=
=C2=A0=C2=A0=C2=A0 0000:00:1f.2
=C2=A077:=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 1243=C2=A0=C2=A0=C2=A0=C2=A0=
=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=
=C2=A0=C2=A0 0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 35447=C2=A0=C2=A0=C2=A0=C2=A0=
=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=
=C2=A0=C2=A0 0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 0=C2=
=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 0=C2=A0 xen-pirq-msi=C2=
=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 radeon
=C2=A078:=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 82521=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=
=C2=A0=C2=A0=C2=A0=C2=A0 0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=
=C2=A0 0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 0=C2=A0=C2=
=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 0=C2=A0=C2=A0=C2=A0=C2=A0=C2=
=A0=C2=A0=C2=A0=C2=A0=C2=A0 0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=
=A0=C2=A0 0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 0=C2=A0 x=
en-pirq-msi=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 xhci_hcd
=C2=A079:=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 23=C2=A0=C2=A0=C2=
=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=
=A0=C2=A0=C2=A0=C2=A0 0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=
=A0 0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 0=C2=A0=C2=A0=
=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=
=C2=A0=C2=A0=C2=A0=C2=A0 0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=
=C2=A0 0=C2=A0 xen-pirq-msi=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 mei_me
=C2=A080:=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 11=C2=A0=C2=A0=C2=
=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=
=A0=C2=A0=C2=A0=C2=A0 0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=
=A0 0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 0=C2=A0=C2=A0=
=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 741=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=
=A0=C2=A0=C2=A0 0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 0=
=C2=A0 xen-pirq-msi=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 em1
=C2=A081:=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 350=C2=A0=C2=A0=C2=A0=
=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=
=C2=A0=C2=A0=C2=A0 0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 =
0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 1671=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=
=A0=C2=A0=C2=A0=C2=A0 0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=
=A0 0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 0=C2=A0 xen-pir=
q-msi=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 iwlwifi
=C2=A082:=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 275=C2=A0=C2=A0=C2=A0=
=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=
=C2=A0=C2=A0=C2=A0 0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 =
0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 0=C2=A0=C2=A0=C2=A0=
=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=
=C2=A0=C2=A0=C2=A0 0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 =
0=C2=A0 xen-pirq-msi=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 snd_hda_intel

With native 3.19 kernel:

Without Dom0 for the same system from the first message:

# cat /proc/interrupts
=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 CPU0=C2=A0=C2=
=A0=C2=A0=C2=A0=C2=A0=C2=A0 CPU1=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 CPU2=
=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 CPU3=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=
=A0 CPU4=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 CPU5=C2=A0=C2=A0=C2=A0=C2=A0=
=C2=A0=C2=A0 CPU6=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 CPU7=C2=A0=C2=A0=C2=
=A0=C2=A0=C2=A0=20
=C2=A0 0:=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 33=C2=A0=C2=A0=C2=
=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=
=A0=C2=A0=C2=A0=C2=A0 0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=
=A0 0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 0=C2=A0=C2=A0=
=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=
=C2=A0=C2=A0=C2=A0=C2=A0 0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=
=C2=A0 0=C2=A0 IR-IO-APIC-edge=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 timer
=C2=A0 8:=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 0=C2=A0=C2=
=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 0=C2=A0=C2=A0=C2=A0=C2=A0=C2=
=A0=C2=A0=C2=A0=C2=A0=C2=A0 0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=
=A0=C2=A0 0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 0=C2=A0=
=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 0=C2=A0=C2=A0=C2=A0=C2=A0=
=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 1=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=
=C2=A0=C2=A0 0=C2=A0 IR-IO-APIC-edge=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 rtc0
=C2=A0 9:=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 20=C2=A0=C2=A0=C2=
=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=
=A0=C2=A0=C2=A0=C2=A0 0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=
=A0 0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 0=C2=A0=C2=A0=
=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 1=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=
=C2=A0=C2=A0=C2=A0=C2=A0 1=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=
=C2=A0 1=C2=A0 IR-IO-APIC-fasteoi=C2=A0=C2=A0 acpi
=C2=A016:=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 15=C2=A0=C2=A0=C2=
=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=
=A0=C2=A0=C2=A0=C2=A0 8=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=
=A0 1=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 4=C2=A0=C2=A0=
=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 1=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=
=C2=A0=C2=A0=C2=A0=C2=A0 1=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=
=C2=A0 1=C2=A0 IR-IO-APIC=C2=A0 16-fasteoi=C2=A0=C2=A0 ehci_hcd:usb3
=C2=A018:=C2=A0=C2=A0=C2=A0=C2=A0 703940=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=
=A0 5678=C2=A0=C2=A0=C2=A0 1426226=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 1303=
=C2=A0=C2=A0=C2=A0 3938243=C2=A0=C2=A0=C2=A0=C2=A0 111477=C2=A0=C2=A0=C2=A0=
=C2=A0 757871=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 510=C2=A0 IR-IO-API=
C=C2=A0 18-fasteoi=C2=A0=C2=A0 ath9k
=C2=A023:=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 11=C2=A0=C2=A0=C2=
=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 2=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=
=A0=C2=A0=C2=A0=C2=A0 3=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=
=A0 0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 0=C2=A0=C2=A0=
=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 17=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=
=C2=A0=C2=A0=C2=A0 2=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 =
0=C2=A0 IR-IO-APIC=C2=A0 23-fasteoi=C2=A0=C2=A0 ehci_hcd:usb4
=C2=A024:=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 0=C2=A0=C2=
=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 0=C2=A0=C2=A0=C2=A0=C2=A0=C2=
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=C2=A0=C2=A0 0=C2=A0 DMAR_MSI-edge=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 dmar0
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=C2=A0=C2=A0 0=C2=A0 DMAR_MSI-edge=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 dmar1
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=C2=A0 1609=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 26822=C2=A0=C2=A0=C2=A0=C2=A0=C2=
=A0=C2=A0=C2=A0 567=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 62281=C2=A0=C2=A0=C2=A0=
=C2=A0=C2=A0=C2=A0 5426=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 14928=C2=A0=C2=A0=C2=
=A0=C2=A0=C2=A0=C2=A0=C2=A0 395=C2=A0 IR-PCI-MSI-edge=C2=A0=C2=A0=C2=A0=C2=
=A0=C2=A0 0000:00:1f.2
=C2=A027:=C2=A0=C2=A0 17977230=C2=A0=C2=A0=C2=A0=C2=A0 628258=C2=A0=C2=A0 4=
4247270=C2=A0=C2=A0=C2=A0=C2=A0 120391 1597809883=C2=A0=C2=A0 14440991=C2=
=A0 152189328=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 73322=C2=A0 IR-PCI-MSI-edge=C2=
=A0=C2=A0=C2=A0=C2=A0=C2=A0 xhci_hcd
=C2=A028:=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 563=C2=A0=C2=A0=C2=A0=
=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=
=C2=A0=C2=A0=C2=A0 0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 =
0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 1=C2=A0=C2=A0=C2=A0=
=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=
=C2=A0=C2=A0=C2=A0 6=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 =
0=C2=A0 IR-PCI-MSI-edge=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 i915
=C2=A029:=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 14=C2=A0=C2=A0=C2=
=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=
=A0=C2=A0=C2=A0=C2=A0 0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=
=A0 4=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 2=C2=A0=C2=A0=
=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 4=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=
=C2=A0=C2=A0=C2=A0=C2=A0 0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=
=C2=A0 0=C2=A0 IR-PCI-MSI-edge=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 mei_me
=C2=A030:=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 39514=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=
=C2=A0 1744=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 60339=C2=A0=C2=A0=C2=A0=C2=A0=C2=
=A0=C2=A0=C2=A0 157=C2=A0=C2=A0=C2=A0=C2=A0 129956=C2=A0=C2=A0=C2=A0=C2=A0=
=C2=A0 19702=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 72140=C2=A0=C2=A0=C2=A0=C2=A0=C2=
=A0=C2=A0=C2=A0=C2=A0 83=C2=A0 IR-PCI-MSI-edge=C2=A0=C2=A0=C2=A0=C2=A0=C2=
=A0 eth0
=C2=A031:=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 3=C2=A0=C2=
=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 0=C2=A0=C2=A0=C2=A0=C2=A0=C2=
=A0=C2=A0=C2=A0=C2=A0=C2=A0 0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=
=A0=C2=A0 1=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 54=C2=A0=C2=A0=
=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=
=C2=A0=C2=A0=C2=A0=C2=A0 0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=
=C2=A0 2=C2=A0 IR-PCI-MSI-edge=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 snd_hda_intel
=C2=A032:=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 28145=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=
=C2=A0=C2=A0 284=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 53316=C2=A0=C2=A0=C2=A0=C2=
=A0=C2=A0=C2=A0=C2=A0=C2=A0 63=C2=A0=C2=A0=C2=A0=C2=A0 139165=C2=A0=C2=A0=
=C2=A0=C2=A0=C2=A0=C2=A0 4410=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 25760=C2=A0=C2=
=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 27=C2=A0 IR-PCI-MSI-edge=C2=A0=C2=
=A0=C2=A0=C2=A0=C2=A0 eth1-rx-0
=C2=A033:=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 1032=C2=A0=C2=A0=C2=A0=C2=A0=
=C2=A0=C2=A0=C2=A0=C2=A0 43=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 2392=C2=A0=
=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 5=C2=A0=C2=A0=C2=A0=C2=A0=
=C2=A0=C2=A0 1797=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 265=C2=A0=C2=A0=
=C2=A0=C2=A0=C2=A0=C2=A0 1507=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=
=A0 20=C2=A0 IR-PCI-MSI-edge=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 eth1-tx-0
=C2=A034:=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 0=C2=A0=C2=
=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 1=C2=A0=C2=A0=C2=A0=C2=A0=C2=
=A0=C2=A0=C2=A0=C2=A0=C2=A0 0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=
=A0=C2=A0 0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 0=C2=A0=
=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 1=C2=A0=C2=A0=C2=A0=C2=A0=
=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 2=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=
=C2=A0=C2=A0 0=C2=A0 IR-PCI-MSI-edge=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 eth1
=C2=A035:=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 5=C2=A0=C2=
=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 0=C2=A0=C2=A0=C2=A0=C2=A0=C2=
=A0=C2=A0=C2=A0=C2=A0=C2=A0 0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=
=A0 12=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 148=C2=A0=C2=A0=C2=A0=C2=
=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 6=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=
=A0=C2=A0=C2=A0 2=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 1=
=C2=A0 IR-PCI-MSI-edge=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 snd_hda_intel


The USB controller is an Intel C210:

00:14.0 USB controller: Intel Corporation 7 Series/C210 Series Chipset Fami=
ly USB xHCI Host Controller (rev 04) (prog-if 30 [XHCI])
=C2=A0=C2=A0=C2=A0 Subsystem: Dell Device 053e
=C2=A0=C2=A0=C2=A0 Flags: bus master, medium devsel, latency 0, IRQ 78
=C2=A0=C2=A0=C2=A0 Memory at f7f20000 (64-bit, non-prefetchable) [size=3D64=
K]
=C2=A0=C2=A0=C2=A0 Capabilities: [70] Power Management version 2
=C2=A0=C2=A0=C2=A0 Capabilities: [80] MSI: Enable+ Count=3D1/8 Maskable- 64=
bit+
=C2=A0=C2=A0=C2=A0 Kernel driver in use: xhci_hcd
=C2=A0=C2=A0=C2=A0 Kernel modules: xhci_pci
     On Tuesday, September 1, 2015 11:50 AM, Ian Campbell <ian.campbell@cit=
rix.com> wrote:
  =20

 On Tue, 2015-09-01 at 13:56 +0000, Justin Acker wrote:
> Thanks Ian,
>=20
> I appreciate the explanation. I believe the device drivers do support=20
> multiple queues when run natively without the Dom0 loaded. The device in=
=20
> question is the xhci_hcd driver for which I/O transfers seem to be slowed=
=20
> when the Dom0 is loaded. The behavior seems to pass through to the DomU=
=20
> if pass through is enabled. I found some similar threads, but most relate=
=20
> to Ethernet controllers. I tried some of the x2apic and x2apic_phys dom0=
=20
> kernel arguments, but none distributed the pirqs. Based on the reading=20
> relating to IRQs for Xen, I think pinning the pirqs to cpu0 is done to=20
> avoid an I/O storm. I tried IRQ balance and when configured/adjusted it=
=20
> will balance individual pirqs, but not multiple interrupts.=20
>=20
> Is there a way to force or enable pirq delivery to a set of cpus as you=
=20
> mentioned above or omit a single device from being a assigned a PIRQ so=
=20
> that its interrupt can be distributed across all cpus?=20

A PIRQ is the way an interrupt is exposed to a PV guest, without it there
would be no interrupt at all.

I'm afraid I'm out of my depth WRT how x86/MSIs and Xen x86/PV pirqs
interact, in particular WRT configuring which set of CPUs can have the IRQ
delivered.

If no one else chimes in soon I'd suggest taking this to the dev list, at
the very least someone who knows what they are talking about (i.e. other
than me) might be able to help.

Ian.



  
------=_Part_1156574_1230247901.1441129186877
Content-Type: text/html; charset=UTF-8
Content-Transfer-Encoding: quoted-printable

<html><body><div style=3D"color:#000; background-color:#fff; font-family:He=
lveticaNeue, Helvetica Neue, Helvetica, Arial, Lucida Grande, sans-serif;fo=
nt-size:16px"><div id=3D"yiv7666178601"><div id=3D"yui_3_16_0_1_14411284073=
58_14706"><div id=3D"yui_3_16_0_1_1441128407358_14705" style=3D"color:#000;=
background-color:#fff;font-family:HelveticaNeue, Helvetica Neue, Helvetica,=
 Arial, Lucida Grande, sans-serif;font-size:16px;"><div id=3D"yiv7666178601=
"><div id=3D"yiv7666178601yui_3_16_0_1_1441128407358_10512"><div id=3D"yiv7=
666178601yui_3_16_0_1_1441128407358_10511" style=3D"color:#000;background-c=
olor:#fff;font-family:HelveticaNeue, Helvetica Neue, Helvetica, Arial, Luci=
da Grande, sans-serif;font-size:16px;">Taking this to the dev list from use=
rs. <br class=3D"" id=3D"yui_3_16_0_1_1441128407358_14820"><br class=3D"" i=
d=3D"yui_3_16_0_1_1441128407358_14828"><div dir=3D"ltr" id=3D"yui_3_16_0_1_=
1441128407358_15195">Is there a way to force or enable pirq delivery to a s=
et of cpus as opposed to single device from being a assigned a single pirq =
so=20
that its interrupt can be distributed across multiple cpus? I believe the d=
evice drivers do support multiple queues when run natively without the Dom0=
 loaded. The device in question is the xhci_hcd driver for which I/O transf=
ers seem to be slowed when the Dom0 is loaded. The behavior seems to pass t=
hrough to the DomU if pass through is enabled. I found some similar threads=
, but most relate to Ethernet controllers. I tried some of the x2apic and x=
2apic_phys dom0 kernel arguments, but none distributed the pirqs. Based on =
the reading relating to IRQs for Xen, I think pinning the pirqs to cpu0 is =
done to avoid an interrupt storm. I tried IRQ balance and when configured/a=
djusted it will balance individual pirqs, but not multiple interrupts.<br c=
lass=3D"" id=3D"yui_3_16_0_1_1441128407358_14832"></div><br class=3D"" id=
=3D"yui_3_16_0_1_1441128407358_14836"><br class=3D"" id=3D"yui_3_16_0_1_144=
1128407358_14838"><br class=3D"" id=3D"yui_3_16_0_1_1441128407358_14840">Wi=
th irqbalance enabled in Dom0:<br class=3D"" id=3D"yui_3_16_0_1_14411284073=
58_14842"><br class=3D"" id=3D"yui_3_16_0_1_1441128407358_14844">&nbsp;&nbs=
p;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; CPU0&nbsp;&nbsp;&nbsp;&n=
bsp;&nbsp;&nbsp; CPU1&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; CPU2&nbsp;&nbsp;&=
nbsp;&nbsp;&nbsp;&nbsp; CPU3&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; CPU4&nbsp;=
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; CPU5&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; CPU=
6&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; CPU7&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; <b=
r class=3D"" id=3D"yui_3_16_0_1_1441128407358_14846">&nbsp;76:&nbsp;&nbsp;&=
nbsp;&nbsp;&nbsp; 11304&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbs=
p; 0&nbsp;&nbsp;&nbsp;&nbsp; 149579&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbs=
p;&nbsp;&nbsp; 0&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 0&nb=
sp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 0&nbsp;&nbsp;&nbsp;&nbs=
p;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 0&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp=
;&nbsp;&nbsp; 0&nbsp; xen-pirq-msi&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 0000=
:00:1f.2<br class=3D"" id=3D"yui_3_16_0_1_1441128407358_14848">&nbsp;77:&nb=
sp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 1243&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&=
nbsp;&nbsp;&nbsp; 0&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 0=
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 35447&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nb=
sp;&nbsp;&nbsp; 0&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 0&n=
bsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 0&nbsp;&nbsp;&nbsp;&nb=
sp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 0&nbsp; xen-pirq-msi&nbsp;&nbsp;&nbsp;&nb=
sp;&nbsp;&nbsp; radeon<br class=3D"" id=3D"yui_3_16_0_1_1441128407358_14850=
">&nbsp;78:&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 82521&nbsp;&nbsp;&nbsp;&nbsp;&nbs=
p;&nbsp;&nbsp;&nbsp;&nbsp; 0&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp=
;&nbsp; 0&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 0&nbsp;&nbs=
p;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 0&nbsp;&nbsp;&nbsp;&nbsp;&nbsp=
;&nbsp;&nbsp;&nbsp;&nbsp; 0&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;=
&nbsp; 0&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 0&nbsp; xen-=
pirq-msi&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; xhci_hcd<br class=3D"" id=3D"y=
ui_3_16_0_1_1441128407358_14852">&nbsp;79:&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nb=
sp;&nbsp;&nbsp; 23&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 0&=
nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 0&nbsp;&nbsp;&nbsp;&n=
bsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 0&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nb=
sp;&nbsp;&nbsp; 0&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 0&n=
bsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 0&nbsp;&nbsp;&nbsp;&nb=
sp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 0&nbsp; xen-pirq-msi&nbsp;&nbsp;&nbsp;&nb=
sp;&nbsp;&nbsp; mei_me<br class=3D"" id=3D"yui_3_16_0_1_1441128407358_14854=
">&nbsp;80:&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 11&nbsp;&nbsp;&=
nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 0&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&n=
bsp;&nbsp;&nbsp;&nbsp; 0&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nb=
sp; 0&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 0&nbsp;&nbsp;&n=
bsp;&nbsp;&nbsp;&nbsp;&nbsp; 741&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&=
nbsp;&nbsp; 0&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 0&nbsp;=
 xen-pirq-msi&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; em1<br class=3D"" id=3D"y=
ui_3_16_0_1_1441128407358_14856">&nbsp;81:&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nb=
sp;&nbsp; 350&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 0&nbsp;=
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 0&nbsp;&nbsp;&nbsp;&nbsp;&=
nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 0&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 1671&nb=
sp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 0&nbsp;&nbsp;&nbsp;&nbs=
p;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 0&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp=
;&nbsp;&nbsp; 0&nbsp; xen-pirq-msi&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; iwlw=
ifi<br class=3D"" id=3D"yui_3_16_0_1_1441128407358_14858">&nbsp;82:&nbsp;&n=
bsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 275&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&=
nbsp;&nbsp;&nbsp; 0&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 0=
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 0&nbsp;&nbsp;&nbsp;&=
nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 0&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&n=
bsp;&nbsp;&nbsp; 0&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 0&=
nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 0&nbsp; xen-pirq-msi&=
nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; snd_hda_intel<br class=3D"" id=3D"yui_3=
_16_0_1_1441128407358_14860"><br class=3D"" id=3D"yui_3_16_0_1_144112840735=
8_14862">With native 3.19 kernel:<br class=3D"" id=3D"yui_3_16_0_1_14411284=
07358_14864"><br class=3D"" id=3D"yui_3_16_0_1_1441128407358_14866">Without=
 Dom0 for the same system from the first message:<br class=3D"" id=3D"yui_3=
_16_0_1_1441128407358_14868"><br class=3D"" id=3D"yui_3_16_0_1_144112840735=
8_14870"># cat /proc/interrupts<br class=3D"" id=3D"yui_3_16_0_1_1441128407=
358_14872">&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; CPU=
0&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; CPU1&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nb=
sp; CPU2&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; CPU3&nbsp;&nbsp;&nbsp;&nbsp;&n=
bsp;&nbsp; CPU4&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; CPU5&nbsp;&nbsp;&nbsp;&=
nbsp;&nbsp;&nbsp; CPU6&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; CPU7&nbsp;&nbsp;=
&nbsp;&nbsp;&nbsp; <br class=3D"" id=3D"yui_3_16_0_1_1441128407358_14874">&=
nbsp; 0:&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 33&nbsp;&nbsp;&nbs=
p;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 0&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp=
;&nbsp;&nbsp;&nbsp; 0&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;=
 0&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 0&nbsp;&nbsp;&nbsp=
;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 0&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;=
&nbsp;&nbsp;&nbsp; 0&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
0&nbsp; IR-IO-APIC-edge&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; timer<br class=3D"" i=
d=3D"yui_3_16_0_1_1441128407358_14876">&nbsp; 8:&nbsp;&nbsp;&nbsp;&nbsp;&nb=
sp;&nbsp;&nbsp;&nbsp;&nbsp; 0&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbs=
p;&nbsp; 0&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 0&nbsp;&nb=
sp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 0&nbsp;&nbsp;&nbsp;&nbsp;&nbs=
p;&nbsp;&nbsp;&nbsp;&nbsp; 0&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp=
;&nbsp; 0&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 1&nbsp;&nbs=
p;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 0&nbsp; IR-IO-APIC-edge&nbsp;&=
nbsp;&nbsp;&nbsp;&nbsp; rtc0<br class=3D"" id=3D"yui_3_16_0_1_1441128407358=
_14878">&nbsp; 9:&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 20&nbsp;&=
nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 0&nbsp;&nbsp;&nbsp;&nbsp;&n=
bsp;&nbsp;&nbsp;&nbsp;&nbsp; 0&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nb=
sp;&nbsp; 0&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 0&nbsp;&n=
bsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 1&nbsp;&nbsp;&nbsp;&nbsp;&nb=
sp;&nbsp;&nbsp;&nbsp;&nbsp; 1&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbs=
p;&nbsp; 1&nbsp; IR-IO-APIC-fasteoi&nbsp;&nbsp; acpi<br class=3D"" id=3D"yu=
i_3_16_0_1_1441128407358_14880">&nbsp;16:&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbs=
p;&nbsp;&nbsp; 15&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 0&n=
bsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 8&nbsp;&nbsp;&nbsp;&nb=
sp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 1&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbs=
p;&nbsp;&nbsp; 4&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 1&nb=
sp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 1&nbsp;&nbsp;&nbsp;&nbs=
p;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 1&nbsp; IR-IO-APIC&nbsp; 16-fasteoi&nbsp;&=
nbsp; ehci_hcd:usb3<br class=3D"" id=3D"yui_3_16_0_1_1441128407358_14882">&=
nbsp;18:&nbsp;&nbsp;&nbsp;&nbsp; 703940&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;=
 5678&nbsp;&nbsp;&nbsp; 1426226&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 1303&nb=
sp;&nbsp;&nbsp; 3938243&nbsp;&nbsp;&nbsp;&nbsp; 111477&nbsp;&nbsp;&nbsp;&nb=
sp; 757871&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 510&nbsp; IR-IO-APIC&n=
bsp; 18-fasteoi&nbsp;&nbsp; ath9k<br class=3D"" id=3D"yui_3_16_0_1_14411284=
07358_14884">&nbsp;23:&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 11&n=
bsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 2&nbsp;&nbsp;&nbsp;&nb=
sp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 3&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbs=
p;&nbsp;&nbsp; 0&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 0&nb=
sp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 17&nbsp;&nbsp;&nbsp;&nbsp;&nb=
sp;&nbsp;&nbsp;&nbsp;&nbsp; 2&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbs=
p;&nbsp; 0&nbsp; IR-IO-APIC&nbsp; 23-fasteoi&nbsp;&nbsp; ehci_hcd:usb4<br c=
lass=3D"" id=3D"yui_3_16_0_1_1441128407358_14886">&nbsp;24:&nbsp;&nbsp;&nbs=
p;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 0&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp=
;&nbsp;&nbsp;&nbsp; 0&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;=
 0&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 0&nbsp;&nbsp;&nbsp=
;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 0&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;=
&nbsp;&nbsp;&nbsp; 0&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
0&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 0&nbsp; DMAR_MSI-ed=
ge&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; dmar0<br class=3D"" id=3D"yui_3_16_0_1_144=
1128407358_14888">&nbsp;25:&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;=
&nbsp; 0&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 0&nbsp;&nbsp=
;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 0&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;=
&nbsp;&nbsp;&nbsp;&nbsp; 0&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&=
nbsp; 0&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 0&nbsp;&nbsp;=
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 0&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&=
nbsp;&nbsp;&nbsp;&nbsp; 0&nbsp; DMAR_MSI-edge&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;=
 dmar1<br class=3D"" id=3D"yui_3_16_0_1_1441128407358_14890">&nbsp;26:&nbsp=
;&nbsp;&nbsp;&nbsp;&nbsp; 20419&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 1609&nb=
sp;&nbsp;&nbsp;&nbsp;&nbsp; 26822&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;=
 567&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 62281&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp=
; 5426&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 14928&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nb=
sp;&nbsp; 395&nbsp; IR-PCI-MSI-edge&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 0000:00:1=
f.2<br class=3D"" id=3D"yui_3_16_0_1_1441128407358_14892">&nbsp;27:&nbsp;&n=
bsp; 17977230&nbsp;&nbsp;&nbsp;&nbsp; 628258&nbsp;&nbsp; 44247270&nbsp;&nbs=
p;&nbsp;&nbsp; 120391 1597809883&nbsp;&nbsp; 14440991&nbsp; 152189328&nbsp;=
&nbsp;&nbsp;&nbsp;&nbsp; 73322&nbsp; IR-PCI-MSI-edge&nbsp;&nbsp;&nbsp;&nbsp=
;&nbsp; xhci_hcd<br class=3D"" id=3D"yui_3_16_0_1_1441128407358_14894">&nbs=
p;28:&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 563&nbsp;&nbsp;&nbsp;&nbsp;=
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 0&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&=
nbsp;&nbsp; 0&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 0&nbsp;=
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 1&nbsp;&nbsp;&nbsp;&nbsp;&=
nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 0&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&n=
bsp;&nbsp; 6&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 0&nbsp; =
IR-PCI-MSI-edge&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; i915<br class=3D"" id=3D"yui_=
3_16_0_1_1441128407358_14896">&nbsp;29:&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;=
&nbsp;&nbsp; 14&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 0&nbs=
p;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 0&nbsp;&nbsp;&nbsp;&nbsp=
;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 4&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;=
&nbsp;&nbsp; 2&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 4&nbsp=
;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 0&nbsp;&nbsp;&nbsp;&nbsp;=
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 0&nbsp; IR-PCI-MSI-edge&nbsp;&nbsp;&nbsp;&nb=
sp;&nbsp; mei_me<br class=3D"" id=3D"yui_3_16_0_1_1441128407358_14898">&nbs=
p;30:&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 39514&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbs=
p; 1744&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 60339&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&n=
bsp;&nbsp; 157&nbsp;&nbsp;&nbsp;&nbsp; 129956&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;=
 19702&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 72140&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nb=
sp;&nbsp;&nbsp; 83&nbsp; IR-PCI-MSI-edge&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; eth0=
<br class=3D"" id=3D"yui_3_16_0_1_1441128407358_14900">&nbsp;31:&nbsp;&nbsp=
;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 3&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;=
&nbsp;&nbsp;&nbsp;&nbsp; 0&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&=
nbsp; 0&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 1&nbsp;&nbsp;=
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 54&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;=
&nbsp;&nbsp;&nbsp; 0&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
0&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 2&nbsp; IR-PCI-MSI-=
edge&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; snd_hda_intel<br class=3D"" id=3D"yui_3_=
16_0_1_1441128407358_14902">&nbsp;32:&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 28145&n=
bsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 284&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
53316&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 63&nbsp;&nbsp;&nbsp;&=
nbsp; 139165&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 4410&nbsp;&nbsp;&nbsp;&nbs=
p;&nbsp; 25760&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 27&nbsp; IR-=
PCI-MSI-edge&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; eth1-rx-0<br class=3D"" id=3D"yu=
i_3_16_0_1_1441128407358_14904">&nbsp;33:&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbs=
p; 1032&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 43&nbsp;&nbsp;&nbsp=
;&nbsp;&nbsp;&nbsp; 2392&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nb=
sp; 5&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 1797&nbsp;&nbsp;&nbsp;&nbsp;&nbsp=
;&nbsp;&nbsp; 265&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 1507&nbsp;&nbsp;&nbsp=
;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 20&nbsp; IR-PCI-MSI-edge&nbsp;&nbsp;&nbsp;&=
nbsp;&nbsp; eth1-tx-0<br class=3D"" id=3D"yui_3_16_0_1_1441128407358_14906"=
>&nbsp;34:&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 0&nbsp;&nb=
sp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 1&nbsp;&nbsp;&nbsp;&nbsp;&nbs=
p;&nbsp;&nbsp;&nbsp;&nbsp; 0&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp=
;&nbsp; 0&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 0&nbsp;&nbs=
p;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 1&nbsp;&nbsp;&nbsp;&nbsp;&nbsp=
;&nbsp;&nbsp;&nbsp;&nbsp; 2&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;=
&nbsp; 0&nbsp; IR-PCI-MSI-edge&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; eth1<br class=
=3D"" id=3D"yui_3_16_0_1_1441128407358_14908">&nbsp;35:&nbsp;&nbsp;&nbsp;&n=
bsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 5&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nb=
sp;&nbsp;&nbsp; 0&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 0&n=
bsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 12&nbsp;&nbsp;&nbsp;&nbsp;&n=
bsp;&nbsp;&nbsp; 148&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
6&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 2&nbsp;&nbsp;&nbsp;=
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 1&nbsp; IR-PCI-MSI-edge&nbsp;&nbsp;&nb=
sp;&nbsp;&nbsp; snd_hda_intel<br class=3D"" id=3D"yui_3_16_0_1_144112840735=
8_14910"><br class=3D"" id=3D"yui_3_16_0_1_1441128407358_14912"><br class=
=3D"" id=3D"yui_3_16_0_1_1441128407358_14914">The USB controller is an Inte=
l C210:<br class=3D"" id=3D"yui_3_16_0_1_1441128407358_14916"><br class=3D"=
" id=3D"yui_3_16_0_1_1441128407358_14918">00:14.0 USB controller: Intel Cor=
poration 7 Series/C210 Series Chipset Family USB xHCI Host Controller (rev =
04) (prog-if 30 [XHCI])<br class=3D"" id=3D"yui_3_16_0_1_1441128407358_1492=
0">&nbsp;&nbsp;&nbsp; Subsystem: Dell Device 053e<br class=3D"" id=3D"yui_3=
_16_0_1_1441128407358_14922">&nbsp;&nbsp;&nbsp; Flags: bus master, medium d=
evsel, latency 0, IRQ 78<br class=3D"" id=3D"yui_3_16_0_1_1441128407358_149=
24">&nbsp;&nbsp;&nbsp; Memory at f7f20000 (64-bit, non-prefetchable) [size=
=3D64K]<br class=3D"" id=3D"yui_3_16_0_1_1441128407358_14926">&nbsp;&nbsp;&=
nbsp; Capabilities: [70] Power Management version 2<br class=3D"" id=3D"yui=
_3_16_0_1_1441128407358_14928">&nbsp;&nbsp;&nbsp; Capabilities: [80] MSI: E=
nable+ Count=3D1/8 Maskable- 64bit+<br class=3D"" id=3D"yui_3_16_0_1_144112=
8407358_14930">&nbsp;&nbsp;&nbsp; Kernel driver in use: xhci_hcd<br class=
=3D"" id=3D"yui_3_16_0_1_1441128407358_14932"><div dir=3D"ltr">&nbsp;&nbsp;=
&nbsp; Kernel modules: xhci_pci</div><div class=3D"yiv7666178601qtdSeparate=
BR" id=3D"yiv7666178601yui_3_16_0_1_1441128407358_5267"><br clear=3D"none">=
</div><div class=3D"yiv7666178601yqt4358837369" id=3D"yiv7666178601yqt68543=
"></div></div></div></div><div class=3D"yiv7666178601yqt5846532267" id=3D"y=
iv7666178601yqt11236"><div id=3D"yiv7666178601yui_3_16_0_1_1441128407358_10=
582"> <div id=3D"yiv7666178601yui_3_16_0_1_1441128407358_5196" style=3D"fon=
t-family:HelveticaNeue, Helvetica Neue, Helvetica, Arial, Lucida Grande, sa=
ns-serif;font-size:16px;"> <div id=3D"yiv7666178601yui_3_16_0_1_14411284073=
58_5195" style=3D"font-family:HelveticaNeue, Helvetica Neue, Helvetica, Ari=
al, Lucida Grande, sans-serif;font-size:16px;"> <div dir=3D"ltr" id=3D"yiv7=
666178601yui_3_16_0_1_1441128407358_5266"> <font id=3D"yiv7666178601yui_3_1=
6_0_1_1441128407358_5265" face=3D"Arial" size=3D"2"> On Tuesday, September =
1, 2015 11:50 AM, Ian Campbell &lt;ian.campbell@citrix.com&gt; wrote:<br cl=
ear=3D"none"> </font> </div>  <br clear=3D"none"><br clear=3D"none"> <div c=
lass=3D"yiv7666178601y_msg_container" id=3D"yiv7666178601yui_3_16_0_1_14411=
28407358_5264">On Tue, 2015-09-01 at 13:56 +0000, Justin Acker wrote:<br cl=
ear=3D"none">&gt; Thanks Ian,<br clear=3D"none">&gt; <br clear=3D"none">&gt=
; I appreciate the explanation. I believe the device drivers do support <br=
 clear=3D"none">&gt; multiple queues when run natively without the Dom0 loa=
ded. The device in <br clear=3D"none">&gt; question is the xhci_hcd driver =
for which I/O transfers seem to be slowed <br clear=3D"none">&gt; when the =
Dom0 is loaded. The behavior seems to pass through to the DomU <br clear=3D=
"none">&gt; if pass through is enabled. I found some similar threads, but m=
ost relate <br clear=3D"none">&gt; to Ethernet controllers. I tried some of=
 the x2apic and x2apic_phys dom0 <br clear=3D"none">&gt; kernel arguments, =
but none distributed the pirqs. Based on the reading <br clear=3D"none">&gt=
; relating to IRQs for Xen, I think pinning the pirqs to cpu0 is done to <b=
r clear=3D"none">&gt; avoid an I/O storm. I tried IRQ balance and when conf=
igured/adjusted it <br clear=3D"none">&gt; will balance individual pirqs, b=
ut not multiple interrupts. <br clear=3D"none">&gt; <br clear=3D"none">&gt;=
 Is there a way to force or enable pirq delivery to a set of cpus as you <b=
r clear=3D"none">&gt; mentioned above or omit a single device from being a =
assigned a PIRQ so <br clear=3D"none">&gt; that its interrupt can be distri=
buted across all cpus? <br clear=3D"none"><br clear=3D"none">A PIRQ is the =
way an interrupt is exposed to a PV guest, without it there<br clear=3D"non=
e">would be no interrupt at all.<br clear=3D"none"><br clear=3D"none">I'm a=
fraid I'm out of my depth WRT how x86/MSIs and Xen x86/PV pirqs<br clear=3D=
"none">interact, in particular WRT configuring which set of CPUs can have t=
he IRQ<br clear=3D"none">delivered.<br clear=3D"none"><br clear=3D"none">If=
 no one else chimes in soon I'd suggest taking this to the dev list, at<br =
clear=3D"none">the very least someone who knows what they are talking about=
 (i.e. other<br clear=3D"none">than me) might be able to help.<div class=3D=
"yiv7666178601yqt5651849718" id=3D"yiv7666178601yqtfd15880"><br clear=3D"no=
ne"><br clear=3D"none">Ian.<br clear=3D"none"><br clear=3D"none"></div><br =
clear=3D"none"><br clear=3D"none"></div>  </div> </div>  </div></div></div>=
</div></div></div></body></html>
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--===============1205095371090951997==
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--===============1205095371090951997==--