From mboxrd@z Thu Jan  1 00:00:00 1970
From: Andrew Cooper <andrew.cooper3@citrix.com>
Subject: Re: [PATCH RESEND v1 5/7] x86: Implement Intel
 Processor Trace context switch
Date: Wed, 2 May 2018 17:51:13 +0100
Message-ID: <86d05029-599e-8fa4-d98c-a340e08297f5@citrix.com>
References: <1516039953-2988-1-git-send-email-luwei.kang@intel.com>
 <1516039953-2988-6-git-send-email-luwei.kang@intel.com>
 <20180426121148.36sxgfj2cjdbkhzn@citrix.com>
 <82D7661F83C1A047AF7DC287873BF1E167F673ED@SHSMSX101.ccr.corp.intel.com>
 <20180502151916.27bz45goyxso674f@citrix.com>
 <5AE9DCA502000078001C037E@prv1-mh.provo.novell.com>
 <20180502161511.mtcsu4zbsyhua7qm@citrix.com>
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To: Wei Liu <wei.liu2@citrix.com>, Jan Beulich <JBeulich@suse.com>
Cc: Kevin Tian <kevin.tian@intel.com>, Stefano Stabellini <sstabellini@kernel.org>, Luwei Kang <luwei.kang@intel.com>, George Dunlap <George.Dunlap@eu.citrix.com>, Tim Deegan <tim@xen.org>, xen-devel@lists.xen.org, Jun Nakajima <jun.nakajima@intel.com>
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