Re: [PATCH v4 05/17] x86emul: support MMX/SSE{, 2, 4a} insns with only register operands

[Andrew Cooper <andrew.cooper3@citrix.com>]

On 28/02/17 12:52, Jan Beulich wrote:
> @@ -2505,12 +2506,21 @@ x86_decode(
>  
>                  opcode |= b | MASK_INSR(vex.pfx, X86EMUL_OPC_PFX_MASK);
>  
> +                if ( !(d & ModRM) )
> +                {
> +                    modrm_reg = modrm_rm = modrm_mod = modrm = 0;
> +                    break;
> +                }
> +
>                  modrm = insn_fetch_type(uint8_t);
>                  modrm_mod = (modrm & 0xc0) >> 6;
>  
>                  break;
>              }
> +    }
>  
> +    if ( d & ModRM )
> +    {
>          modrm_reg = ((rex_prefix & 4) << 1) | ((modrm & 0x38) >> 3);
>          modrm_rm  = modrm & 0x07;
>  

Doesn't this hunk want splitting out into its own patch and
backporting?  Xen 4.8's x86_decode_insn() was supposedly able to provide
the correct length.

If so, both patches Reviewed-by: Andrew Cooper <andrew.cooper3@citrix.com>

> @@ -5658,6 +5668,18 @@ x86_emulate(
>      CASE_SIMD_PACKED_FP(_VEX, 0x0f, 0x50): /* vmovmskp{s,d} {x,y}mm,reg */
>      CASE_SIMD_PACKED_INT(0x0f, 0xd7):      /* pmovmskb {,x}mm,reg */
>      case X86EMUL_OPC_VEX_66(0x0f, 0xd7):   /* vpmovmskb {x,y}mm,reg */
> +        opc = init_prefixes(stub);
> +        opc[0] = b;
> +        /* Convert GPR destination to %rAX. */
> +        rex_prefix &= ~REX_R;
> +        vex.r = 1;
> +        if ( !mode_64bit() )
> +            vex.w = 0;
> +        opc[1] = modrm & 0xc7;

As an observation, converting GPR to %rAX is also becoming a common
sequence.

~Andrew

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