From mboxrd@z Thu Jan 1 00:00:00 1970 From: Justin Acker Subject: Re: xhci_hcd intterrupt affinity in Dom0/DomU limited to single interrupt Date: Wed, 2 Sep 2015 17:25:20 +0000 (UTC) Message-ID: <940090229.496270.1441214720241.JavaMail.yahoo@mail.yahoo.com> References: <55E6FDD9.1090301@citrix.com> Reply-To: Justin Acker Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============1502668813747619505==" Return-path: In-Reply-To: <55E6FDD9.1090301@citrix.com> List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org To: David Vrabel , "xen-devel@lists.xen.org" List-Id: xen-devel@lists.xenproject.org --===============1502668813747619505== Content-Type: multipart/alternative; boundary="----=_Part_496269_798741857.1441214720237" Content-Length: 3509 ------=_Part_496269_798741857.1441214720237 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit From: David Vrabel To: Justin Acker ; "xen-devel@lists.xen.org" Sent: Wednesday, September 2, 2015 9:47 AM Subject: Re: [Xen-devel] xhci_hcd intterrupt affinity in Dom0/DomU limited to single interrupt On 01/09/15 18:39, Justin Acker wrote: > Taking this to the dev list from users. > > Is there a way to force or enable pirq delivery to a set of cpus as > opposed to single device from being a assigned a single pirq so that its > interrupt can be distributed across multiple cpus? No. PIRQs are delivered via event channels and these can only be bound to one VCPU at a time. Thanks David. This applies to Dom0 or Dom0/DomU? David ------=_Part_496269_798741857.1441214720237 Content-Type: text/html; charset=UTF-8 Content-Transfer-Encoding: quoted-printable

From: David Vrabel <david.vrabel@citrix.com>
To: Justin Acker <ackerj67@yahoo.com&= gt;; "xen-devel@lists.xen.org" <xen-devel@lists.xen.org>
Sent: Wednesday, September= 2, 2015 9:47 AM
Subject:<= /b> Re: [Xen-devel] xhci_hcd intterrupt affinity in Dom0/DomU limited to si= ngle interrupt

On 01/09/15 18:39, Justin Acker wrote:


> Taking this to the dev list from users.=
>
> Is there a way to force or = enable pirq delivery to a set of cpus as
> opposed to = single device from being a assigned a single pirq so that its
> interrupt can be distributed across multiple cpus?


No.

PIRQs= are delivered via event channels and these can only be bound to
one VCPU at a time.

Thanks David. This applies to Dom0 or Dom0/DomU?

David



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