[PATCH v2] x86: Use deep C states for off-lined CPUs

[Boris Ostrovsky <boris.ostrovsky@amd.com>]

# HG changeset patch
# User Boris Ostrovsky <boris.ostrovsky@amd.com>
# Date 1330642361 -3600
# Node ID 99df5c6b2964ceaa73651d7bc02fb1ae820f7691
# Parent  a7bacdc5449a2f7bb9c35b2a1334b463fe9f29a9
x86: Use deep C states for off-lined CPUs

Currently when a core is taken off-line it is placed in C1 state (unless
MONITOR/MWAIT is used). This patch allows a core to go to deeper C states
resulting in significantly higher power savings.

Signed-off-by: Boris Ostrovsky <boris.ostrovsky@amd.com>

diff -r a7bacdc5449a -r 99df5c6b2964 xen/arch/x86/acpi/cpu_idle.c
--- a/xen/arch/x86/acpi/cpu_idle.c	Mon Feb 27 17:05:18 2012 +0000
+++ b/xen/arch/x86/acpi/cpu_idle.c	Thu Mar 01 23:52:41 2012 +0100
@@ -566,6 +566,7 @@ static void acpi_dead_idle(void)
     struct acpi_processor_power *power;
     struct acpi_processor_cx *cx;
     void *mwait_ptr;
+    struct cpuinfo_x86 *c = &current_cpu_data;
 
     if ( (power = processor_powers[smp_processor_id()]) == NULL )
         goto default_halt;
@@ -601,6 +602,23 @@ static void acpi_dead_idle(void)
             mb();
             __mwait(cx->address, 0);
         }
+    } 
+    else if ( c->x86_vendor == X86_VENDOR_AMD && 
+              cx->entry_method == ACPI_CSTATE_EM_SYSIO )
+    {
+        /* Intel prefers not to use SYSIO */
+
+        /* Avoid references to shared data after the cache flush */
+        u32 address = cx->address;
+        u32 pmtmr_ioport_local = pmtmr_ioport;
+
+        wbinvd();
+
+        while ( 1 )
+        {
+            inb(address);
+            inl(pmtmr_ioport_local);
+        }
     }
 
 default_halt: