From: Julien Grall <julien.grall@linaro.org>
To: Manish Jaggi <mjaggi@caviumnetworks.com>,
marc.zyngier@arm.com, sstabellini@kernel.org, jgross@suse.com,
xen-devel@lists.xenproject.org
Cc: manish.jaggi@cavium.com
Subject: Re: [PATCH 01/12] arm:Kconfig Rename menu text
Date: Thu, 15 Mar 2018 11:25:12 +0000 [thread overview]
Message-ID: <9a46effb-36e0-e828-d213-b96b2ee50d1f@linaro.org> (raw)
In-Reply-To: <7b9852b6-a630-8ba5-3105-91524eabcd33@caviumnetworks.com>
On 15/03/18 06:10, Manish Jaggi wrote:
>
> Hi Julien,
>
> On 03/13/2018 05:45 PM, Julien Grall wrote:
>> Hi,
>>
>> On 12/03/18 12:42, mjaggi@caviumnetworks.com wrote:
>>> From: Manish Jaggi <manish.jaggi@cavium.com>
>>>
>>> Rename the menu text to Errata Workarounds. Subsequent patches will
>>> add config options for SoC specific erratas.
>>
>> Well, your SoC is an Arm SoC, right? So what is the benefits of this
>> new name? M
> It was based on your last comment
>
> "I would much prefer to see the memu "ARM errata workaround via..."
> renamed to "Errata Workarounds". So we have only one menu with all
> workarounds."
I am fully aware that I suggested that patch. However, you still have to
add a minimum of rationale in the commit message to understand why the
rename. You have other people on that mailing list to look at patches...
>
>
>> ore that it still depends on HAS_ALTERNATIVE.
> check_workaroundXXX depends on it. So I kept it as is.
HAS_ALTERNATIVE is used by both arm32 and arm64.
>
> If you think this patch is not required, I can drop it.
The way it is does not make sense. I would prefer to drop it for now and
just focus on the vGIC errata.
Cheers,
--
Julien Grall
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next prev parent reply other threads:[~2018-03-15 11:25 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-03-12 12:42 [PATCH 00/12] arm64: Mediate access to GICv3 sysregs at EL2 mjaggi
2018-03-12 12:42 ` [PATCH 01/12] arm:Kconfig Rename menu text mjaggi
2018-03-13 12:15 ` Julien Grall
2018-03-15 6:10 ` Manish Jaggi
2018-03-15 11:25 ` Julien Grall [this message]
2018-03-12 12:42 ` [PATCH 02/12] arm64: cputype: Add MIDR values for Cavium ThunderX1 CPUs mjaggi
2018-03-13 12:17 ` Julien Grall
2018-03-12 12:42 ` [PATCH 03/12] arm64: Add config for Cavium Thunder erratum 30115 mjaggi
2018-03-13 12:23 ` Julien Grall
2018-03-12 12:42 ` [PATCH 04/12] Enable Group1 Traps by default for Cavium ThunderX1 mjaggi
2018-03-13 12:27 ` Julien Grall
2018-03-12 12:42 ` [PATCH 05/12] Placeholder for handling Group1 register traps mjaggi
2018-03-13 14:30 ` Julien Grall
2018-03-12 12:42 ` [PATCH 06/12] arm64: vgic-v3: Add ICV_BPR1_EL1 handler mjaggi
2018-03-12 12:42 ` [PATCH 07/12] arm64: vgic-v3: Add ICV_IGRPEN1_EL1 handler mjaggi
2018-03-12 12:42 ` [PATCH 08/12] arm64: Add accessors for the ICH_APxRn_EL2 registers mjaggi
2018-03-12 12:42 ` [PATCH 09/12] Expose ich_read/write_lr in vsysreg_errata.c mjaggi
2018-03-13 14:31 ` Julien Grall
2018-03-12 12:42 ` [PATCH 10/12] arm64: Add ICV_IAR1_EL1 handler mjaggi
2018-03-12 12:42 ` [PATCH 11/12] arm64: vgic-v3: Add ICV_EOIR1_EL1 handler mjaggi
2018-03-12 12:42 ` [PATCH 12/12] arm64: vgic-v3: Add ICV_HPPIR1_EL1 handler mjaggi
2018-03-12 12:58 ` [PATCH 00/12] arm64: Mediate access to GICv3 sysregs at EL2 Marc Zyngier
2018-03-13 12:14 ` Julien Grall
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