From mboxrd@z Thu Jan  1 00:00:00 1970
From: Keir Fraser <keir.xen@gmail.com>
Subject: Re: [PATCH][RFC] FPU LWP 0/5: patch description
Date: Thu, 14 Apr 2011 22:09:59 +0100
Message-ID: <C9CD2137.16600%keir.xen@gmail.com>
References: <4DA75B07.6010503@amd.com>
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To: Wei Huang <wei.huang2@amd.com>, "'xen-devel@lists.xensource.com'" <xen-devel@lists.xensource.com>
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On 14/04/2011 21:37, "Wei Huang" <wei.huang2@amd.com> wrote:

> The following patches support AMD lightweight profiling.
> 
> Because LWP isn't tracked by CR0.TS bit, we clean up the FPU code to
> handle lazy and unlazy FPU states differently. Lazy FPU state (such as
> SSE, YMM) is handled when #NM is triggered. Unlazy state, such as LWP,
> is saved and restored on each vcpu context switch. To simplify the code,
> we also add a mask option to xsave/xrstor function.

How much cost is added to context switch paths in the (overwhelmingly
likely) case that LWP is not being used by the guest? Is this adding a whole
lot of unconditional overhead for a feature that noone uses?

 -- Keir

> Thanks,
> -Wei
> 
> 
> 
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