From: Keir Fraser <keir.xen@gmail.com>
To: Tim Deegan <tim@xen.org>, Andrew Cooper <andrew.cooper3@citrix.com>
Cc: George Dunlap <George.Dunlap@eu.citrix.com>,
xen-devel@lists.xensource.com
Subject: Re: AMD IOMMU intremap tables and IOAPICs
Date: Tue, 06 Sep 2011 17:13:07 +0100 [thread overview]
Message-ID: <CA8C0523.2061D%keir.xen@gmail.com> (raw)
In-Reply-To: <20110906160612.GA12835@ocelot.phlegethon.org>
On 06/09/2011 17:06, "Tim Deegan" <tim@xen.org> wrote:
> At 16:54 +0100 on 06 Sep (1315328056), Andrew Cooper wrote:
>> On 06/09/11 16:47, George Dunlap wrote:
>>> Wei,
>>>
>>> Quick question: Am I reading the code correctly, that even with
>>> per-device interrupt remap tables, that GSIs are accounted to the
>>> intremap table of the corresponding IOAPIC, presumably because the
>>> IOMMU sees interrupts generated as GSIs as coming from the IOAPIC? In
>>> that case, then we need all devices sharing the same IOAPIC must not
>>> have any vector collisions. Is that correct?
>>
>> Based on the ICH10 IO-APIC documentation with respect to auto EOIs, we
>> cant have any two IRQs across any IO-APICs sharing a vector,
>> irrespective of IOMMU or not. (Because the EOI'ing an IO-APIC entry
>> only takes account of vector and not destination)
>
> If this is the case, is there any point in having per-CPU IDTs?
> Or per-device remapping tables?
It still makes sense for MSIs, which are the most common interrupt type
these days.
-- Keir
> Tim.
>
> _______________________________________________
> Xen-devel mailing list
> Xen-devel@lists.xensource.com
> http://lists.xensource.com/xen-devel
next prev parent reply other threads:[~2011-09-06 16:13 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2011-09-06 15:47 AMD IOMMU intremap tables and IOAPICs George Dunlap
2011-09-06 15:54 ` Andrew Cooper
2011-09-06 15:57 ` George Dunlap
2011-09-06 16:03 ` Andrew Cooper
2011-09-06 16:00 ` George Dunlap
2011-09-06 16:06 ` Tim Deegan
2011-09-06 16:03 ` George Dunlap
2011-09-06 16:13 ` Keir Fraser [this message]
2011-09-06 16:25 ` Andrew Cooper
2011-09-07 11:18 ` Wei Wang2
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