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From: Bhupinder Thakur <bhupinder.thakur@linaro.org>
To: Andre Przywara <andre.przywara@linaro.org>
Cc: Xen-devel <xen-devel@lists.xenproject.org>,
	Julien Grall <julien.grall@linaro.org>,
	Stefano Stabellini <sstabellini@kernel.org>,
	Dave Martin <dave.martin@arm.com>
Subject: Re: [PATCH RFC] ARM: vPL011: use receive timeout interrupt
Date: Tue, 24 Oct 2017 18:26:42 +0530	[thread overview]
Message-ID: <CACtJ1JTV2VFQtCnZ60kroeZX_g004fuxmYoYUSUt072SNb_GoQ@mail.gmail.com> (raw)
In-Reply-To: <42732370-9edf-9086-1ad3-23590577ca80@linaro.org>

Hi Andre,


On 24 October 2017 at 16:57, Andre Przywara <andre.przywara@linaro.org> wrote:
> Hi,
>
> On 24/10/17 12:00, Julien Grall wrote:
>> Hi,
>>
>> On 23/10/2017 17:01, Andre Przywara wrote:
>>> Hi,
>>>
>>> On 18/10/17 17:32, Bhupinder Thakur wrote:
>>>> Hi Andre,
>>>>
>>>> I verified this patch on qualcomm platform. It is working fine.
>>>>
>>>> On 18 October 2017 at 19:11, Andre Przywara <andre.przywara@arm.com>
>>>> wrote:
>>>>> Instead of asserting the receive interrupt (RXI) on the first character
>>>>> in the FIFO, lets (ab)use the receive timeout interrupt (RTI) for that
>>>>> purpose. That seems to be closer to the spec and what hardware does.
>>>>> Improve the readability of vpl011_data_avail() on the way.
>>>>>
>>>>> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
>>>>> ---
>>>>> Hi,
>>>>>
>>>>> this one is the approach I mentioned in the email earlier today.
>>>>> It goes on top of Bhupinders v12 27/27, but should eventually be merged
>>>>> into this one once we agreed on the subject. I just carved it out here
>>>>> for clarity to make it clearer what has been changed.
>>>>> Would be good if someone could test it.
>>>>>
>>>>> Cheers,
>>>>> Andre.
>>>>>  xen/arch/arm/vpl011.c | 61
>>>>> ++++++++++++++++++++++++---------------------------
>>>>>  1 file changed, 29 insertions(+), 32 deletions(-)
>>>>>
>>>>> diff --git a/xen/arch/arm/vpl011.c b/xen/arch/arm/vpl011.c
>>>>> index adf1711571..ae18bddd81 100644
>>>>> --- a/xen/arch/arm/vpl011.c
>>>>> +++ b/xen/arch/arm/vpl011.c
>>>>> @@ -105,9 +105,13 @@ static uint8_t vpl011_read_data(struct domain *d)
>>>>>          if ( fifo_level == 0 )
>>>>>          {
>>>>>              vpl011->uartfr |= RXFE;
>>>>> -            vpl011->uartris &= ~RXI;
>>>>> -            vpl011_update_interrupt_status(d);
>>>>> +            vpl011->uartris &= ~RTI;
>>>>>          }
>>>>> +
>>>>> +        if ( fifo_level < sizeof(intf->in) - SBSA_UART_FIFO_SIZE / 2 )
>>>>> +            vpl011->uartris &= ~RXI;
>>>>> +
>>>>> +        vpl011_update_interrupt_status(d);
>>>> I think we check if ( fifo_level < SBSA_UART_FIFO_SIZE / 2 ) which
>>>> should be a valid condition to clear the RX interrupt.
>>>
>>> Are you sure? My understanding is that the semantics of the return value
>>> of xencons_queued() differs between intf and outf:
>>> - For intf, Xen fills that buffer with incoming characters. The
>>> watermark is assumed to be (FIFO / 2), which translates into 16
>>> characters. Now for the SBSA vUART RX side that means: "Assert the RX
>>> interrupt if there is only room for 16 (or less) characters in the FIFO
>>> (read: intf buffer in our case). Since we (ab)use the Xen buffer for the
>>> FIFO, this means we warn if the number of queued characters exceeds
>>> (buffersize - 16).
>>> - For outf, the UART emulation fills the buffer. The SBSA vUART TX side
>>> demands that the TX interrupt is asserted if the fill level of the
>>> transmit FIFO is less than or equal to the 16 characters, which means:
>>> number of queued characters is less than 16.
>>>
>>> I think the key point is that our trigger level isn't symmetrical here,
>>> since we have to emulate the architected 32-byte FIFO semantics for the
>>> driver, but have a (secretly) much larger "FIFO" internally.
>>>
>>> Do you agree with this reasoning and do I have a thinko here? Could well
>>> be I am seriously misguided here.
>>
>> xencons_queued calculates how many bytes are currently on the ring. So I
>> think your description makes sense.
>>
>> With (fifo_level < (SBSA_UART_FIFO_SIZE / 2)), you would only clear it
>> when the ring has less than 16 bytes queued.
>>
>> I have a few requests on those patches for the resender:
>>     - Please introduce a define for SBSA_UART_FIFO_SIZE / 2 and use it
>> everywhere.
>>     - Please add a bit more documentation on top of the checks in
>> vpl011_read_data function. The checks in vpl011_write_data looks
>> well-documented.
>
> I am just at rewording the commit message and was planning on re-sending
> the (merged) patches later today (keeping Bhupinder's authorship, of
> course).
>
> I hope that Bhupinder doesn't mind or this doesn't clash with any of his
> plans.
It is fine with me. Thanks.

Regards,
Bhupinder

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  reply	other threads:[~2017-10-24 12:56 UTC|newest]

Thread overview: 20+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-10-13 10:40 [PATCH 26/27 v12] arm/xen: vpl011: Fix the slow early console SBSA UART output Bhupinder Thakur
2017-10-13 10:40 ` [PATCH 27/27 v12] arm/xen: vpl011: Correct the logic for asserting/de-asserting SBSA UART TX interrupt Bhupinder Thakur
2017-10-13 13:59   ` Dave Martin
2017-10-18 10:26   ` Andre Przywara
2017-10-18 10:47     ` Bhupinder Thakur
2017-10-18 13:41     ` [PATCH RFC] ARM: vPL011: use receive timeout interrupt Andre Przywara
2017-10-18 16:32       ` Bhupinder Thakur
2017-10-23 16:01         ` Andre Przywara
2017-10-24 11:00           ` Julien Grall
2017-10-24 11:27             ` Andre Przywara
2017-10-24 12:56               ` Bhupinder Thakur [this message]
2017-10-24 12:56           ` Bhupinder Thakur
2017-10-17  9:51 ` [PATCH 26/27 v12] arm/xen: vpl011: Fix the slow early console SBSA UART output Andre Przywara
2017-10-17 11:19   ` Dave Martin
2017-10-17 12:53     ` Rob Herring
2017-10-17 13:44       ` Dave Martin
2017-10-17 14:03         ` Russell King - ARM Linux
2017-10-17 14:49           ` Dave P Martin
2017-10-18 10:17   ` Bhupinder Thakur
2017-10-18 10:31     ` Andre Przywara

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