Re: [PATCH] xc_cpuid_x86.c: No need to mask NX twice

[z <alfred.z.song@gmail.com>]

[-- Attachment #1.1: Type: text/plain, Size: 5856 bytes --]

On Mon, Sep 8, 2014 at 5:09 PM, Jan Beulich <JBeulich@suse.com> wrote:

> >>> On 08.09.14 at 10:48, <alfred.z.song@gmail.com> wrote:
>
> Things look fine from a general pov, but
>
> > @@ -278,12 +274,14 @@ static void xc_cpuid_hvm_policy(
> >      DECLARE_DOMCTL;
> >      char brand[13];
> >      uint64_t val;
> > -    int is_pae, is_nestedhvm;
> > +    int is_64bit, is_pae, is_nestedhvm;
> >      uint64_t xfeature_mask;
> >
> >      xc_hvm_param_get(xch, domid, HVM_PARAM_PAE_ENABLED, &val);
> >      is_pae = !!val;
> > -
> > +
> > +    is_64bit = hypervisor_is_64bit(xch) && is_pae;
>
> ... with this using hypervisor_is_64bit() and there not being a 32-bit
> hypervisor anymore, there's clearly room for more cleanup (and in
> particular no need to pass around an "is_64bit" variable that's always
> going to be set to true).
>

Do your mean hypervisor_is_64bit() will always return true? Then it means
that is_64bit will only depend on is_pae here, so we could simply use
is_pae instead of is_64bit in both vendor specific functions.  If so, I
think xen_64bit in xc_cpuid_pv_policy could also be dropped and
function hypervisor_is_64bit()
is also redundant now. Right?

Maybe something like this?

diff --git a/tools/libxc/xc_cpuid_x86.c b/tools/libxc/xc_cpuid_x86.c
index 6b81641..710fd61 100644
--- a/tools/libxc/xc_cpuid_x86.c
+++ b/tools/libxc/xc_cpuid_x86.c
@@ -34,13 +34,6 @@
 #define DEF_MAX_INTELEXT  0x80000008u
 #define DEF_MAX_AMDEXT    0x8000001cu

-static int hypervisor_is_64bit(xc_interface *xch)
-{
-    xen_capabilities_info_t xen_caps = "";
-    return ((xc_version(xch, XENVER_capabilities, &xen_caps) == 0) &&
-            (strstr(xen_caps, "x86_64") != NULL));
-}
-
 static void cpuid(const unsigned int *input, unsigned int *regs)
 {
     unsigned int count = (input[1] == XEN_CPUID_INPUT_UNUSED) ? 0 :
input[1];
@@ -95,13 +88,11 @@ static void amd_xc_cpuid_policy(
         break;

     case 0x80000001: {
-        int is_64bit = hypervisor_is_64bit(xch) && is_pae;
-
         if ( !is_pae )
             clear_bit(X86_FEATURE_PAE, regs[3]);

         /* Filter all other features according to a whitelist. */
-        regs[2] &= ((is_64bit ? bitmaskof(X86_FEATURE_LAHF_LM) : 0) |
+        regs[2] &= (bitmaskof(X86_FEATURE_LAHF_LM) |
                     bitmaskof(X86_FEATURE_CMP_LEGACY) |
                     (is_nestedhvm ? bitmaskof(X86_FEATURE_SVM) : 0) |
                     bitmaskof(X86_FEATURE_CR8_LEGACY) |
@@ -116,8 +107,8 @@ static void amd_xc_cpuid_policy(
                     bitmaskof(X86_FEATURE_TBM) |
                     bitmaskof(X86_FEATURE_DBEXT));
         regs[3] &= (0x0183f3ff | /* features shared with 0x00000001:EDX */
-                    (is_pae ? bitmaskof(X86_FEATURE_NX) : 0) |
-                    (is_64bit ? bitmaskof(X86_FEATURE_LM) : 0) |
+                    bitmaskof(X86_FEATURE_NX) |
+                    bitmaskof(X86_FEATURE_LM) |
                     bitmaskof(X86_FEATURE_SYSCALL) |
                     bitmaskof(X86_FEATURE_MP) |
                     bitmaskof(X86_FEATURE_MMXEXT) |
@@ -195,16 +186,14 @@ static void intel_xc_cpuid_policy(
         break;

     case 0x80000001: {
-        int is_64bit = hypervisor_is_64bit(xch) && is_pae;
-
         /* Only a few features are advertised in Intel's 0x80000001. */
-        regs[2] &= (is_64bit ? bitmaskof(X86_FEATURE_LAHF_LM) : 0) |
-                               bitmaskof(X86_FEATURE_3DNOWPREFETCH) |
-                               bitmaskof(X86_FEATURE_ABM);
-        regs[3] &= ((is_pae ? bitmaskof(X86_FEATURE_NX) : 0) |
-                    (is_64bit ? bitmaskof(X86_FEATURE_LM) : 0) |
-                    (is_64bit ? bitmaskof(X86_FEATURE_SYSCALL) : 0) |
-                    (is_64bit ? bitmaskof(X86_FEATURE_RDTSCP) : 0));
+        regs[2] &= (bitmaskof(X86_FEATURE_LAHF_LM) |
+                    bitmaskof(X86_FEATURE_3DNOWPREFETCH) |
+                    bitmaskof(X86_FEATURE_ABM);
+        regs[3] &= (bitmaskof(X86_FEATURE_NX) |
+                    bitmaskof(X86_FEATURE_LM) |
+                    (is_pae ? bitmaskof(X86_FEATURE_SYSCALL) : 0) |
+                    (is_pae ? bitmaskof(X86_FEATURE_RDTSCP) : 0));
         break;
     }

@@ -392,6 +381,8 @@ static void xc_cpuid_hvm_policy(

     case 0x80000001:
         if ( !is_pae ) {
+            clear_bit(X86_FEATURE_LAHF_LM, regs[2]);
+            clear_bit(X86_FEATURE_LM, regs[3]);
             clear_bit(X86_FEATURE_NX, regs[3]);
             clear_bit(X86_FEATURE_PSE36, regs[3]);
         }
@@ -442,7 +433,7 @@ static void xc_cpuid_pv_policy(
 {
     DECLARE_DOMCTL;
     unsigned int guest_width;
-    int guest_64bit, xen_64bit = hypervisor_is_64bit(xch);
+    int guest_64bit;
     char brand[13];
     uint64_t xfeature_mask;

@@ -474,7 +465,7 @@ static void xc_cpuid_pv_policy(
     switch ( input[0] )
     {
     case 0x00000001:
-        if ( !xen_64bit || strstr(brand, "AMD") )
+        if ( strstr(brand, "AMD") )
             clear_bit(X86_FEATURE_SEP, regs[3]);
         clear_bit(X86_FEATURE_DS, regs[3]);
         clear_bit(X86_FEATURE_ACC, regs[3]);



Zhuo


> > @@ -391,10 +389,18 @@ static void xc_cpuid_hvm_policy(
> >          break;
> >
> >      case 0x80000001:
> > -        if ( !is_pae ) {
> > +        if ( !is_64bit ) {
> > +            clear_bit(X86_FEATURE_LAHF_LM, regs[2]);
> > +            clear_bit(X86_FEATURE_LM, regs[3]);
> > +            clear_bit(X86_FEATURE_NX, regs[3]);
> > +            clear_bit(X86_FEATURE_PSE36, regs[3]);
> > +        } else if ( !is_pae ) {
> >              clear_bit(X86_FEATURE_NX, regs[3]);
> >              clear_bit(X86_FEATURE_PSE36, regs[3]);
> > +        } else {
> > +            /* Do nothing for 32-bit guest */
> >          }
>
> The ordering of the if/else-if above seems wrong to me, but this
> would become moot anyway if "is_64bit" got dropped.
>
> Jan
>
>

[-- Attachment #1.2: Type: text/html, Size: 8191 bytes --]

[-- Attachment #2: Type: text/plain, Size: 126 bytes --]

_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xen.org
http://lists.xen.org/xen-devel