From mboxrd@z Thu Jan  1 00:00:00 1970
From: "G.R." <firemeteor@users.sourceforge.net>
Subject: Re: Need help to debug win7 BSOD on IGD passthrough
Date: Mon, 21 Jan 2013 00:26:00 +0800
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To: Stefano Stabellini <stefano.stabellini@eu.citrix.com>
Cc: Ian Jackson <Ian.Jackson@eu.citrix.com>, Ross Philipson <Ross.Philipson@citrix.com>, Jean Guyader <jean.guyader@gmail.com>, xen-devel <xen-devel@lists.xen.org>
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On Wed, Jan 16, 2013 at 2:40 AM, Stefano Stabellini
<stefano.stabellini@eu.citrix.com> wrote:
>> PS: it looks that the switch-on-address style of code is not very robust.
>> This would fail if the guest access using unexpected alignment && length.
>> I guess may be we should switch to a mask based implementation.
>
> Given the way QEMU emulates the PCI config space, I don't think is
> possible to receive a reads or writes with a length different from 1, 2 or
> 4 bytes.
> However I am always open to code improvements.

I'm not sure if I understand the QEMU part. But at least I've seen
this in the log:

igd_pci_read: [00:00:0] addr=0 len=4 val=1508086
igd_pci_read: [00:00:0] addr=4 len=4 val=20900006
igd_pci_read: [00:00:0] addr=8 len=4 val=6000009
igd_pci_read: [00:00:0] addr=c len=4 val=0

igd_pci_read: [00:00:0] addr=6 len=2 val=2090
igd_pci_read: [00:00:0] addr=34 len=1 val=e0
igd_pci_read: [00:00:0] addr=e0 len=2 val=9
igd_pci_read: [00:00:0] addr=4 len=2 val=6
igd_pci_read: [00:00:0] addr=4 len=2 val=6
igd_pci_read: [00:00:0] addr=c len=1 val=0
igd_pci_read: [00:00:0] addr=d len=1 val=0

There are both 2 && 4 bytes read to offset 0x4, and 2 bytes read to offset 0x6.
If we only check for 0x6 in igd_pci_read(), the 4-byte read to offset
0x4 would show inconsistent result.
But I'm not sure if this matters to SW.