From mboxrd@z Thu Jan  1 00:00:00 1970
From: Keir Fraser <keir.xen@gmail.com>
Subject: Re: [PATCH] x86: refine FPU selector handling code for
	XSAVEOPT
Date: Mon, 05 Aug 2013 17:03:38 +0100
Message-ID: <CE258B6A.2F342%keir.xen@gmail.com>
References: <51FFBF2902000078000E9492@nat28.tlf.novell.com>
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To: Jan Beulich <JBeulich@suse.com>, xen-devel <xen-devel@lists.xen.org>
Cc: Ben Guthro <ben.guthro@gmail.com>
List-Id: xen-devel@lists.xenproject.org

On 05/08/2013 14:05, "Jan Beulich" <JBeulich@suse.com> wrote:

> Some extra tweaks are necessary to deal with the situation of XSAVEOPT
> not writing the FPU portion of the save image (due to it detecting that
> the register state did not get modified since the last XRSTOR).
> 
> Signed-off-by: Jan Beulich <jbeulich@suse.com>
> Tested-by: Ben Guthro <ben.guthro@gmail.com>

Acked-by: Keir Fraser <keir@xen.org>

> --- a/xen/arch/x86/xstate.c
> +++ b/xen/arch/x86/xstate.c
> @@ -71,10 +71,28 @@ void xsave(struct vcpu *v, uint64_t mask
>  
>      if ( word_size <= 0 || !is_pv_32bit_vcpu(v) )
>      {
> +        typeof(ptr->fpu_sse.fip.sel) fcs = ptr->fpu_sse.fip.sel;
> +        typeof(ptr->fpu_sse.fdp.sel) fds = ptr->fpu_sse.fdp.sel;
> +
>          if ( cpu_has_xsaveopt )
> +        {
> +            /*
> +             * xsaveopt may not write the FPU portion even when the
> respective
> +             * mask bit is set. For the check further down to work we hence
> +             * need to put the save image back into the state that it was in
> +             * right after the previous xsaveopt.
> +             */
> +            if ( word_size > 0 &&
> +                 (ptr->fpu_sse.x[FPU_WORD_SIZE_OFFSET] == 4 ||
> +                  ptr->fpu_sse.x[FPU_WORD_SIZE_OFFSET] == 2) )
> +            {
> +                ptr->fpu_sse.fip.sel = 0;
> +                ptr->fpu_sse.fdp.sel = 0;
> +            }
>              asm volatile ( ".byte 0x48,0x0f,0xae,0x37"
>                             : "=m" (*ptr)
>                             : "a" (lmask), "d" (hmask), "D" (ptr) );
> +        }
>          else
>              asm volatile ( ".byte 0x48,0x0f,0xae,0x27"
>                             : "=m" (*ptr)
> @@ -87,7 +105,14 @@ void xsave(struct vcpu *v, uint64_t mask
>                */
>               (!(ptr->fpu_sse.fsw & 0x0080) &&
>                boot_cpu_data.x86_vendor == X86_VENDOR_AMD) )
> +        {
> +            if ( cpu_has_xsaveopt && word_size > 0 )
> +            {
> +                ptr->fpu_sse.fip.sel = fcs;
> +                ptr->fpu_sse.fdp.sel = fds;
> +            }
>              return;
> +        }
>  
>          if ( word_size > 0 &&
>               !((ptr->fpu_sse.fip.addr | ptr->fpu_sse.fdp.addr) >> 32) )
> 
> 
>