From: Andrew Cooper <andrew.cooper3@citrix.com>
To: Suravee Suthikulpanit <Suravee.Suthikulpanit@amd.com>,
xen-devel@lists.xen.org
Cc: boris.ostrovsky@oracle.com, jbeulich@suse.com, sherry.hurwitz@amd.com
Subject: Re: [PATCH v2 05/10] x86/HVM/SVM: Add AVIC initialization code
Date: Wed, 4 Jan 2017 17:59:53 +0000 [thread overview]
Message-ID: <a51d9a2d-805e-2aa4-d1b8-9da534f77ed0@citrix.com> (raw)
In-Reply-To: <5f20d5f2-bc8e-500b-5820-71a08fce5fe6@amd.com>
On 04/01/17 17:24, Suravee Suthikulpanit wrote:
> On 1/2/17 23:37, Andrew Cooper wrote:
>>> +
>>> + vmcb->avic_bk_pg_pa = page_to_maddr(vlapic->regs_page) &
>>> AVIC_HPA_MASK;
>>
>> This use of AVIC_HPA_MASK may truncate the the address, which is
>> definitely a problem.
>
> I'm not quite sure that I got the truncation that you pointed out.
> Could you please elaborate?
My apologies. I hadn't considered the PAGE_SHIFT in the definition, and
had come to the conclusion you were chopping the physical address off at
2^40.
>
>> If AVIC_HPA_MASK isn't just related to maxphysaddr, then you need to
>> pass appropriate memflags into the alloc_domheap_page() calls to get a
>> suitable page.
>>
>
> If by "maxphysaddr" is the 52-bit physical address limit for the PAE
> mode, then I think that's related.
You can safely rely on page_to_maddr() giving you a sensible value
without further masking. By having a struct_page in the first place, it
is a known good frame.
>
>>> +
>>> + entry = *(s->avic_last_phy_id);
>>> + smp_rmb();
>>> + entry.bk_pg_ptr = (vmcb->avic_bk_pg_pa & AVIC_HPA_MASK) >>
>>> AVIC_HPA_SHIFT;
>>> + entry.is_running = 0;
>>> + entry.valid = 1;
>>> + *(s->avic_last_phy_id) = entry;
>>> + smp_wmb();
>>
>> During domain creation, no guests are running, so you can edit this
>> cleanly.
> >
>> What values are actually being excluded here? This, and other patches,
>> look like you are actually just trying to do a read_atomic(), modify,
>> write_atomic() update, rather than actually requiring ordering.
>>
>
> Besides the read_atomic(), modify write_atomic() to update the entry.
> I also want to make sure that the compiler won't shuffle the order
> around, which I thought can be achieved via smp_rmb() and smp_wmb().
Shuffle which order? Your smp_rmb() is between two writes, and the
smp_wmb() isn't paired with anything.
I think using read_atomic() and write_atomic() will DTRT for you; All
you appear to need is a guarantee that the code won't read/update the
live table using multiple accesses.
~Andrew
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next prev parent reply other threads:[~2017-01-04 17:59 UTC|newest]
Thread overview: 48+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-12-31 5:45 [PATCH v2 00/10] Introduce AMD SVM AVIC Suravee Suthikulpanit
2016-12-31 5:45 ` [PATCH v2 01/10] x86/HVM: Introduce struct hvm_pi_ops Suravee Suthikulpanit
2017-01-05 2:54 ` Tian, Kevin
2017-01-05 7:57 ` Jan Beulich
2017-01-05 15:51 ` Jan Beulich
2017-01-10 6:51 ` Suravee Suthikulpanit
2017-01-10 8:24 ` Jan Beulich
2017-01-10 9:45 ` Suravee Suthikulpanit
2016-12-31 5:45 ` [PATCH v2 02/10] x86/vLAPIC: Declare vlapic_read_aligned() and vlapic_reg_write() as non-static Suravee Suthikulpanit
2017-01-05 15:53 ` Jan Beulich
2017-01-10 6:57 ` Suravee Suthikulpanit
2017-01-10 8:25 ` Jan Beulich
2016-12-31 5:45 ` [PATCH v2 03/10] x86/HVM: Call vlapic_destroy after vcpu_destroy Suravee Suthikulpanit
2017-01-05 2:56 ` Tian, Kevin
2017-01-05 15:56 ` Jan Beulich
2017-01-10 8:18 ` Suravee Suthikulpanit
2016-12-31 5:45 ` [PATCH v2 04/10] x86/SVM: Modify VMCB fields to add AVIC support Suravee Suthikulpanit
2016-12-31 5:45 ` [PATCH v2 05/10] x86/HVM/SVM: Add AVIC initialization code Suravee Suthikulpanit
2017-01-02 16:37 ` Andrew Cooper
2017-01-04 17:24 ` Suravee Suthikulpanit
2017-01-04 17:59 ` Andrew Cooper [this message]
2017-01-10 3:06 ` Suravee Suthikulpanit
2017-01-03 14:54 ` Boris Ostrovsky
2016-12-31 5:45 ` [PATCH v2 06/10] x86/SVM: Add AVIC vmexit handlers Suravee Suthikulpanit
2017-01-02 17:28 ` Andrew Cooper
2017-01-05 4:07 ` Suravee Suthikulpanit
2017-01-03 15:34 ` Boris Ostrovsky
2017-01-05 6:41 ` Suravee Suthikulpanit
2016-12-31 5:45 ` [PATCH v2 07/10] x86/SVM: Add vcpu scheduling support for AVIC Suravee Suthikulpanit
2017-01-02 17:35 ` Andrew Cooper
2017-01-03 15:43 ` Boris Ostrovsky
2016-12-31 5:45 ` [PATCH v2 08/10] x86/SVM: Add interrupt management code via AVIC Suravee Suthikulpanit
2017-01-02 17:45 ` Andrew Cooper
2017-02-28 12:01 ` George Dunlap
2017-01-05 16:01 ` Jan Beulich
2016-12-31 5:46 ` [PATCH v2 09/10] x86/SVM: Hook up miscellaneous AVIC functions Suravee Suthikulpanit
2017-01-02 17:49 ` Andrew Cooper
2017-01-05 16:05 ` Jan Beulich
2017-01-10 8:35 ` Suravee Suthikulpanit
2017-01-10 9:00 ` Jan Beulich
2017-01-10 10:28 ` Suravee Suthikulpanit
2016-12-31 5:46 ` [PATCH v2 10/10] x86/SVM: Add AMD AVIC key handler Suravee Suthikulpanit
2017-01-03 16:01 ` Boris Ostrovsky
2017-01-03 16:04 ` Andrew Cooper
2017-01-05 8:00 ` Suravee Suthikulpanit
2017-01-05 16:07 ` Jan Beulich
2017-01-10 11:14 ` Suravee Suthikulpanit
2017-01-10 12:55 ` Jan Beulich
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