From: Julien Grall <julien.grall@arm.com>
To: Andre Przywara <andre.przywara@arm.com>,
Stefano Stabellini <sstabellini@kernel.org>
Cc: xen-devel@lists.xenproject.org
Subject: Re: [PATCH v4 25/27] ARM: vITS: create and initialize virtual ITSes for Dom0
Date: Tue, 4 Apr 2017 18:03:47 +0100 [thread overview]
Message-ID: <a961d151-09d8-668c-9b5c-3e380a3e2b08@arm.com> (raw)
In-Reply-To: <20170403202829.7278-26-andre.przywara@arm.com>
Hi Andre,
On 03/04/17 21:28, Andre Przywara wrote:
> For each hardware ITS create and initialize a virtual ITS for Dom0.
> We use the same memory mapped address to keep the doorbell working.
>
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
> ---
> xen/arch/arm/vgic-v3-its.c | 32 ++++++++++++++++++++++++++++++++
> xen/arch/arm/vgic-v3.c | 17 +++++++++++++++++
> xen/include/asm-arm/domain.h | 1 +
> xen/include/asm-arm/gic_v3_its.h | 16 ++++++++++++++++
> 4 files changed, 66 insertions(+)
>
> diff --git a/xen/arch/arm/vgic-v3-its.c b/xen/arch/arm/vgic-v3-its.c
> index 35a0730..dfb6eb3 100644
> --- a/xen/arch/arm/vgic-v3-its.c
> +++ b/xen/arch/arm/vgic-v3-its.c
> @@ -1080,6 +1080,38 @@ static const struct mmio_handler_ops vgic_its_mmio_handler = {
> .write = vgic_v3_its_mmio_write,
> };
>
> +int vgic_v3_its_init_virtual(struct domain *d, paddr_t guest_addr,
> + unsigned int devid_bits, unsigned int intid_bits)
*All* initialization functions should have a counterpart in the same
patch to free the memory.
> +{
> + struct virt_its *its;
> + uint64_t base_attr;
> +
> + its = xzalloc(struct virt_its);
> + if ( ! its )
> + return -ENOMEM;
> +
> + base_attr = GIC_BASER_InnerShareable << GITS_BASER_SHAREABILITY_SHIFT;
> + base_attr |= GIC_BASER_CACHE_SameAsInner << GITS_BASER_OUTER_CACHEABILITY_SHIFT;
> + base_attr |= GIC_BASER_CACHE_RaWaWb << GITS_BASER_INNER_CACHEABILITY_SHIFT;
> +
> + its->cbaser = base_attr;
> + base_attr |= 0ULL << GITS_BASER_PAGE_SIZE_SHIFT;
Please explain the 0ULL.
> + its->baser_dev = GITS_BASER_TYPE_DEVICE << GITS_BASER_TYPE_SHIFT;
> + its->baser_dev |= (7ULL << GITS_BASER_ENTRY_SIZE_SHIFT) | base_attr;
Please explain 7ULL. I suspect you can use a sizeof of the device structure.
> + its->baser_coll = GITS_BASER_TYPE_COLLECTION << GITS_BASER_TYPE_SHIFT;
> + its->baser_coll |= (1ULL << GITS_BASER_ENTRY_SIZE_SHIFT) | base_attr;
Please explain 1ULL. I suspect you can use a sizeof of the collection
structure.
> + its->d = d;
> + its->doorbell_address = guest_addr + ITS_DOORBELL_OFFSET;
> + its->devid_bits = devid_bits;
> + its->intid_bits = intid_bits;
> + spin_lock_init(&its->vcmd_lock);
> + spin_lock_init(&its->its_lock);
> +
> + register_mmio_handler(d, &vgic_its_mmio_handler, guest_addr, SZ_64K, its);
> +
> + return 0;
> +}
> +
> /*
> * Local variables:
> * mode: C
> diff --git a/xen/arch/arm/vgic-v3.c b/xen/arch/arm/vgic-v3.c
> index ebcfc16..3fc309e 100644
> --- a/xen/arch/arm/vgic-v3.c
> +++ b/xen/arch/arm/vgic-v3.c
> @@ -30,6 +30,7 @@
> #include <asm/current.h>
> #include <asm/mmio.h>
> #include <asm/gic_v3_defs.h>
> +#include <asm/gic_v3_its.h>
> #include <asm/vgic.h>
> #include <asm/vgic-emul.h>
> #include <asm/vreg.h>
> @@ -1582,6 +1583,7 @@ static int vgic_v3_domain_init(struct domain *d)
> */
> if ( is_hardware_domain(d) )
> {
> + struct host_its *hw_its;
> unsigned int first_cpu = 0;
>
> d->arch.vgic.dbase = vgic_v3_hw.dbase;
> @@ -1607,6 +1609,21 @@ static int vgic_v3_domain_init(struct domain *d)
>
> first_cpu += size / d->arch.vgic.rdist_stride;
> }
> + d->arch.vgic.nr_regions = vgic_v3_hw.nr_rdist_regions;
Why did you add that?
> +
> + list_for_each_entry(hw_its, &host_its_list, entry)
This could be done in vgic-v3-its.c. Also, I would prefer to see
something similar to vgic_v3_setup_hw for ITS to make the code agnostic.
> + {
> + /*
Coding style.
> + * For each host ITS create a virtual ITS using the same
> + * base and thus doorbell address.
> + * Use the same number of device ID bits as the host, and
> + * allow 20 bits for the interrupt ID.
Why only 20? This sounds like a made up number that will not fit some
platform... For the hardware domain you should the same value as used
for the host ITS.
> + */
> + vgic_v3_its_init_virtual(d, hw_its->addr, hw_its->devid_bits, 20);
Please check the return value.
> +
> + d->arch.vgic.has_its = true;
> + }
> +
> }
> else
> {
> diff --git a/xen/include/asm-arm/domain.h b/xen/include/asm-arm/domain.h
> index f460457..6a60630 100644
> --- a/xen/include/asm-arm/domain.h
> +++ b/xen/include/asm-arm/domain.h
> @@ -115,6 +115,7 @@ struct arch_domain
> spinlock_t its_devices_lock; /* Protects the its_devices tree */
> struct radix_tree_root pend_lpi_tree; /* Stores struct pending_irq's */
> rwlock_t pend_lpi_tree_lock; /* Protects the pend_lpi_tree */
> + bool has_its;
> #endif
> } vgic;
>
> diff --git a/xen/include/asm-arm/gic_v3_its.h b/xen/include/asm-arm/gic_v3_its.h
> index 3b5f898..fb05311 100644
> --- a/xen/include/asm-arm/gic_v3_its.h
> +++ b/xen/include/asm-arm/gic_v3_its.h
> @@ -154,6 +154,14 @@ uint64_t gicv3_get_redist_address(unsigned int cpu, bool use_pta);
> int gicv3_its_setup_collection(unsigned int cpu);
>
> /*
> + * Create and register a virtual ITS at the given guest address.
> + * If a host ITS is specified, a hardware domain can reach out to that host
> + * ITS to deal with devices and LPI mappings and can enable/disable LPIs.
> + */
> +int vgic_v3_its_init_virtual(struct domain *d, paddr_t guest_addr,
> + unsigned int devid_bits, unsigned int intid_bits);
> +
> +/*
> * Map a device on the host by allocating an ITT on the host (ITS).
> * "nr_event" specifies how many events (interrupts) this device will need.
> * Setting "valid" to false deallocates the device.
> @@ -219,6 +227,14 @@ static inline void gicv3_its_unmap_all_devices(struct domain *d)
> {
> }
>
> +static inline int vgic_v3_its_init_virtual(struct domain *d,
> + paddr_t guest_addr,
> + unsigned int devid_bits,
> + unsigned int intid_bits)
> +{
> + return 0;
> +}
> +
> #endif /* CONFIG_HAS_ITS */
>
> #endif
>
Cheers,
--
Julien Grall
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next prev parent reply other threads:[~2017-04-04 17:03 UTC|newest]
Thread overview: 57+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-04-03 20:28 [PATCH v4 00/27] arm64: Dom0 ITS emulation Andre Przywara
2017-04-03 20:28 ` [PATCH v4 01/27] ARM: GICv3 ITS: parse and store ITS subnodes from hardware DT Andre Przywara
2017-04-05 0:40 ` Stefano Stabellini
2017-04-03 20:28 ` [PATCH v4 02/27] ARM: GICv3 ITS: initialize host ITS Andre Przywara
2017-04-03 21:03 ` Julien Grall
2017-04-03 20:28 ` [PATCH v4 03/27] ARM: GICv3: allocate LPI pending and property table Andre Przywara
2017-04-03 21:47 ` Julien Grall
2017-04-03 20:28 ` [PATCH v4 04/27] ARM: GICv3 ITS: allocate device and collection table Andre Przywara
2017-04-05 0:56 ` Stefano Stabellini
2017-04-03 20:28 ` [PATCH v4 05/27] ARM: GICv3 ITS: map ITS command buffer Andre Przywara
2017-04-03 21:56 ` Julien Grall
2017-04-03 20:28 ` [PATCH v4 06/27] ARM: GICv3 ITS: introduce ITS command handling Andre Przywara
2017-04-03 22:39 ` Julien Grall
2017-04-03 20:28 ` [PATCH v4 07/27] ARM: GICv3 ITS: introduce host LPI array Andre Przywara
2017-04-03 23:07 ` Julien Grall
2017-04-04 10:40 ` Julien Grall
2017-04-03 20:28 ` [PATCH v4 08/27] ARM: GICv3 ITS: introduce device mapping Andre Przywara
2017-04-04 9:03 ` Julien Grall
2017-04-04 16:13 ` Julien Grall
2017-04-03 20:28 ` [PATCH v4 09/27] ARM: GICv3: introduce separate pending_irq structs for LPIs Andre Przywara
2017-04-04 11:43 ` Julien Grall
2017-04-03 20:28 ` [PATCH v4 10/27] ARM: GICv3: forward pending LPIs to guests Andre Przywara
2017-04-04 11:55 ` Julien Grall
2017-04-04 15:36 ` Julien Grall
2017-04-03 20:28 ` [PATCH v4 11/27] ARM: GICv3: enable ITS and LPIs on the host Andre Przywara
2017-04-03 20:28 ` [PATCH v4 12/27] ARM: vGICv3: handle virtual LPI pending and property tables Andre Przywara
2017-04-04 13:01 ` Julien Grall
2017-04-03 20:28 ` [PATCH v4 13/27] ARM: vGICv3: Handle disabled LPIs Andre Przywara
2017-04-03 20:28 ` [PATCH v4 14/27] ARM: vGICv3: introduce basic ITS emulation bits Andre Przywara
2017-04-04 13:35 ` Julien Grall
2017-04-03 20:28 ` [PATCH v4 15/27] ARM: vITS: introduce translation table walks Andre Przywara
2017-04-04 15:59 ` Julien Grall
2017-04-03 20:28 ` [PATCH v4 16/27] ARM: vITS: handle CLEAR command Andre Przywara
2017-04-04 16:03 ` Julien Grall
2017-04-03 20:28 ` [PATCH v4 17/27] ARM: vITS: handle INT command Andre Przywara
2017-04-04 16:05 ` Julien Grall
2017-04-03 20:28 ` [PATCH v4 18/27] ARM: vITS: handle MAPC command Andre Przywara
2017-04-04 16:08 ` Julien Grall
2017-04-03 20:28 ` [PATCH v4 19/27] ARM: vITS: handle MAPD command Andre Przywara
2017-04-04 16:09 ` Julien Grall
2017-04-03 20:28 ` [PATCH v4 20/27] ARM: vITS: handle MAPTI command Andre Przywara
2017-04-04 16:22 ` Julien Grall
2017-04-03 20:28 ` [PATCH v4 21/27] ARM: vITS: handle MOVI command Andre Przywara
2017-04-04 16:37 ` Julien Grall
2017-04-03 20:28 ` [PATCH v4 22/27] ARM: vITS: handle DISCARD command Andre Przywara
2017-04-04 16:40 ` Julien Grall
2017-04-03 20:28 ` [PATCH v4 23/27] ARM: vITS: handle INV command Andre Przywara
2017-04-04 16:51 ` Julien Grall
2017-04-05 23:21 ` André Przywara
2017-04-03 20:28 ` [PATCH v4 24/27] ARM: vITS: handle INVALL command Andre Przywara
2017-04-04 17:00 ` Julien Grall
2017-04-03 20:28 ` [PATCH v4 25/27] ARM: vITS: create and initialize virtual ITSes for Dom0 Andre Przywara
2017-04-04 17:03 ` Julien Grall [this message]
2017-04-03 20:28 ` [PATCH v4 26/27] ARM: vITS: create ITS subnodes for Dom0 DT Andre Przywara
2017-04-03 20:28 ` [PATCH v4 27/27] ARM: vGIC: advertise LPI support Andre Przywara
2017-04-05 13:06 ` Julien Grall
2017-04-04 12:36 ` [PATCH v4 00/27] arm64: Dom0 ITS emulation Julien Grall
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