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a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1789145447; h=from:from:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=mNCCwd+rbPqirfm0wkJvjXVhjTPI0RhTanYIYxdf+Sc=; b=dyTb5RIXj6qSDD92B+97mEGjfUaOXS+hdK5xDPdPEkAZ21B73SXDBWiYnLv9ZlUcw9cmv6 cKk7U2rZNIuZSXuISELFfD/iMVZpj3GzRUTo1aNXh+5Zx8YVtIXDZgVC6+3Ak4a1MflGIv wBnWCkHKNaxh4X5Do//8fxnQEk3k8QA= X-MC-Unique: uChttM2tMFKEHHKjELXc6g-1 X-Mimecast-MFC-AGG-ID: uChttM2tMFKEHHKjELXc6g_1789145442 Date: Fri, 11 Sep 2026 17:50:37 +0100 From: Daniel =?utf-8?B?UC4gQmVycmFuZ8Op?= To: qemu-devel@nongnu.org Cc: xen-devel@lists.xenproject.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, qemu-block@nongnu.org, qemu-s390x@nongnu.org, qemu-arm@nongnu.org Subject: Re: [PATCH 15/28] hw: define most common PCI types as secure Message-ID: Reply-To: Daniel =?utf-8?B?UC4gQmVycmFuZ8Op?= References: <20260911143627.2743803-1-berrange@redhat.com> <20260911143627.2743803-16-berrange@redhat.com> MIME-Version: 1.0 In-Reply-To: <20260911143627.2743803-16-berrange@redhat.com> User-Agent: Mutt/2.4.0 (2026-06-19) X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.111 X-Mimecast-MFC-PROC-ID: 00KBXM8MZ-mTLYm3esJMocm6rDivbMrd7fVa8zd7AQ8_1789145442 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit X-purgate-ID: tlsNG-33051d/1789145449-758824E9-CFC4269C/0/0 X-purgate-type: clean X-purgate-size: 2465 On Fri, Sep 11, 2026 at 03:36:14PM +0100, Daniel P. Berrangé wrote: > Essentially all PCI infrastructure is in scope for the virtualization > use case, aside from the niche simba bridge. > > Signed-off-by: Daniel P. Berrangé > --- > hw/pci-bridge/gen_pcie_root_port.c | 1 + > hw/pci-bridge/i82801b11.c | 1 + > hw/pci-bridge/ioh3420.c | 1 + > hw/pci-bridge/pci_bridge_dev.c | 2 ++ > hw/pci-bridge/pci_expander_bridge.c | 8 ++++++++ > hw/pci-bridge/pcie_pci_bridge.c | 1 + > hw/pci-bridge/pcie_root_port.c | 1 + > hw/pci-bridge/xio3130_downstream.c | 1 + > hw/pci-bridge/xio3130_upstream.c | 1 + > hw/pci/pci.c | 7 +++++++ > hw/pci/pci_bridge.c | 1 + > hw/pci/pci_host.c | 1 + > hw/pci/pcie_host.c | 1 + > hw/pci/pcie_port.c | 1 + > 14 files changed, 28 insertions(+) > > diff --git a/hw/pci-bridge/pci_expander_bridge.c b/hw/pci-bridge/pci_expander_bridge.c > index 40ffbc4e08..bd5598b639 100644 > --- a/hw/pci-bridge/pci_expander_bridge.c > +++ b/hw/pci-bridge/pci_expander_bridge.c snip > @@ -128,6 +130,7 @@ static const TypeInfo pxb_cxl_bus_info = { > .parent = TYPE_CXL_BUS, > .instance_size = sizeof(PXBBus), > .class_init = pxb_bus_class_init, > + .secure = true, > }; > snip > static void pxb_cxl_realize(DeviceState *dev, Error **errp) > @@ -249,6 +253,7 @@ static const TypeInfo cxl_host_info = { > .parent = TYPE_PCI_HOST_BRIDGE, > .instance_size = sizeof(CXLHost), > .class_init = pxb_cxl_host_class_init, > + .secure = true, > }; > > /* snip > @@ -540,6 +547,7 @@ static const TypeInfo pxb_cxl_dev_info = { > .parent = TYPE_PXB_PCIE_DEV, > .instance_size = sizeof(PXBCXLDev), > .class_init = pxb_cxl_dev_class_init, > + .secure = true, > .interfaces = > (const InterfaceInfo[]){ > { INTERFACE_CONVENTIONAL_PCI_DEVICE }, These three were a mistake. No CXL code is intended to be classed as secure at this time. With regards, Daniel -- |: https://berrange.com ~~ https://hachyderm.io/@berrange :| |: https://libvirt.org ~~ https://entangle-photo.org :| |: https://pixelfed.art/berrange ~~ https://fstop138.berrange.com :|