From: Boris Ostrovsky <boris.ostrovsky@oracle.com>
To: Andrew Cooper <andrew.cooper3@citrix.com>,
Yi Sun <yi.y.sun@linux.intel.com>,
xen-devel@lists.xenproject.org
Cc: kevin.tian@intel.com, wei.liu2@citrix.com,
dario.faggioli@citrix.com, ian.jackson@eu.citrix.com,
mengxu@cis.upenn.edu, jbeulich@suse.com,
chao.p.peng@linux.intel.com, roger.pau@citrix.com
Subject: Re: [PATCH v15 00/23] Enable L2 Cache Allocation Technology & Refactor psr.c
Date: Thu, 3 Aug 2017 18:50:02 -0400 [thread overview]
Message-ID: <baa7bd55-9c45-b2c5-8769-859bb9e7c2bf@oracle.com> (raw)
In-Reply-To: <73215889-8896-f075-c49b-a1d1849813ac@citrix.com>
On 08/03/2017 11:37 AM, Andrew Cooper wrote:
> On 01/08/17 09:48, Yi Sun wrote:
>> Hi all,
>>
>> We plan to bring a new PSR (Platform Shared Resource) feature called
>> Intel L2 Cache Allocation Technology (L2 CAT) to Xen. It has been enabled
>> in Linux Kernel.
>
> Unfortunately, the result is problematic. This is from XenServers basic
> sanity testing.
>
> (XEN) [ 1071.542192] Assertion 'socket_info' failed at psr.c:1297
> (XEN) [ 1071.542202] ----[ Xen-4.10.0-xs139419-d x86_64 debug=y Not tainted ]----
> (XEN) [ 1071.542207] CPU: 14
> (XEN) [ 1071.542211] RIP: e008:[<ffff82d0802a948f>] psr_domain_free+0x23/0xcc
> (XEN) [ 1071.542223] RFLAGS: 0000000000010246 CONTEXT: hypervisor
> (XEN) [ 1071.542229] rax: 0000000000000000 rbx: ffff8308291c8000 rcx: 00000000004016c2
> (XEN) [ 1071.542235] rdx: ffff831005317fff rsi: 0000000000000000 rdi: ffff8308291c8000
> (XEN) [ 1071.542241] rbp: ffff831005317da0 rsp: ffff831005317d70 r8: 0000000000000000
> (XEN) [ 1071.542246] r9: 0000000000000001 r10: 0200000000000000 r11: 0000000000000001
> (XEN) [ 1071.542252] r12: 00000000ffffffff r13: ffff8308291c8aa8 r14: ffff8308291c8000
> (XEN) [ 1071.542258] r15: ffff830829988000 cr0: 000000008005003b cr4: 00000000000426e0
> (XEN) [ 1071.542263] cr3: 00000000cce80000 cr2: ffff88000234d298
> (XEN) [ 1071.542268] ds: 002b es: 002b fs: 0000 gs: 0000 ss: e010 cs: e008
> (XEN) [ 1071.542276] Xen code around <ffff82d0802a948f> (psr_domain_free+0x23/0xcc):
> (XEN) [ 1071.542280] 3d a3 70 1c 00 00 75 02 <0f> 0b 49 83 be 60 09 00 00 00 0f 84 89 00 00 00
> (XEN) [ 1071.542299] Xen stack trace from rsp=ffff831005317d70:
> (XEN) [ 1071.542302] ffff8308291c8000 ffff8308291c8000 00000000ffffffff ffff8308291c8aa8
> (XEN) [ 1071.542311] ffff8308291c8000 ffff830829988000 ffff831005317dc0 ffff82d08027cc31
> (XEN) [ 1071.542321] ffff8308291c8aa8 ffff8300cd159000 ffff831005317df0 ffff82d0802080f7
> (XEN) [ 1071.542365] ffff8308299b0040 0000000000000000 0000000000000000 ffff831005317fff
> (XEN) [ 1071.542372] ffff831005317e20 ffff82d08022a86f ffff82d08059ab00 ffff82d08059b200
> (XEN) [ 1071.542380] ffff82d08059ab00 fffffffffffffffd ffff831005317e50 ffff82d08023b75f
> (XEN) [ 1071.542389] 000000000000000e ffff8308299af670 ffff8308299af748 000000000000000e
> (XEN) [ 1071.542396] ffff831005317e60 ffff82d08023b79f ffff831005317ee0 ffff82d0802d792f
> (XEN) [ 1071.542405] ffff82d080365cb3 ffff82d08059b200 ffff82d08059ab00 ffffffffffffffff
> (XEN) [ 1071.542413] ffff831005317fff 0000000000000000 0000000000000000 00001fcc00001f07
> (XEN) [ 1071.542420] 000000000000000e 000000000000000e ffff82d0805e4b10 ffff831005317fff
> (XEN) [ 1071.542428] 000000000000000e ffff830829988000 ffff831005317f10 ffff82d08027b6dc
> (XEN) [ 1071.542436] ffff830829923000 ffff8300cd2e7000 ffff8300cd1ee000 ffff830829923000
> (XEN) [ 1071.542444] ffff831005317da8 ffff880131e40000 0000000000000000 0000000000000000
> (XEN) [ 1071.542452] 000000000000000e ffff880131e43eb8 ffffffff81ae5878 0000000000000246
> (XEN) [ 1071.542459] 0000000000007ff0 ffff8800c653f921 0000000000000000 0000000000000000
> (XEN) [ 1071.542467] ffffffff810013aa ffffffff81a40bc0 deadbeefdeadf00d deadbeefdeadf00d
> (XEN) [ 1071.542475] 0000010000000000 ffffffff810013aa 000000000000e033 0000000000000246
> (XEN) [ 1071.542483] ffff880131e43ea0 000000000000e02b c2c2c2c2c2c2c2c2 c2c2c2c2c2c2c2c2
> (XEN) [ 1071.542491] c2c2c2c2c2c2c2c2 c2c2c2c2c2c2c2c2 c2c2c2c20000000e ffff8300cd2e7000
> (XEN) [ 1071.542500] Xen call trace:
> (XEN) [ 1071.542505] [<ffff82d0802a948f>] psr_domain_free+0x23/0xcc
> (XEN) [ 1071.542514] [<ffff82d08027cc31>] arch_domain_destroy+0x88/0x8f
> (XEN) [ 1071.542521] [<ffff82d0802080f7>] domain.c#complete_domain_destroy+0x6f/0x192
> (XEN) [ 1071.542528] [<ffff82d08022a86f>] rcupdate.c#rcu_process_callbacks+0x141/0x1a3
> (XEN) [ 1071.542536] [<ffff82d08023b75f>] softirq.c#__do_softirq+0x7f/0x8a
> (XEN) [ 1071.542542] [<ffff82d08023b79f>] process_pending_softirqs+0x35/0x37
> (XEN) [ 1071.542551] [<ffff82d0802d792f>] mwait-idle.c#mwait_idle+0xfc/0x2dd
> (XEN) [ 1071.542557] [<ffff82d08027b6dc>] domain.c#idle_loop+0x72/0x8a
> (XEN) [ 1071.542561]
> (XEN) [ 1071.916649]
> (XEN) [ 1071.918881] ****************************************
> (XEN) [ 1071.924987] Panic on CPU 14:
> (XEN) [ 1071.928771] Assertion 'socket_info' failed at psr.c:1297
> (XEN) [ 1071.935265] ****************************************
> (XEN) [ 1071.941375]
> (XEN) [ 1071.943606] Reboot in five seconds...
>
> The hardware is SandyBridge-EN, which has no PSR support as far as I am aware. As a first thought, psr_free_domain() should not be making any assertions about hardware state.
Not surprisingly, I hit this as well.
It seems to me that socket_info is set only if "psr" boot parameter is
explicitly set *and* opt_cos_max is not sufficiently low. So ASSERT()
should be either turned into 'if' or possibly be swapped with
d->arch.psr_cos_ids test.
-boris
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next prev parent reply other threads:[~2017-08-03 22:50 UTC|newest]
Thread overview: 43+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-08-01 8:48 [PATCH v15 00/23] Enable L2 Cache Allocation Technology & Refactor psr.c Yi Sun
2017-08-01 8:48 ` [PATCH v15 01/23] docs: create Cache Allocation Technology (CAT) and Code and Data Prioritization (CDP) feature document Yi Sun
2017-08-03 12:26 ` Wei Liu
2017-08-04 4:40 ` Yi Sun
2017-08-04 11:56 ` Wei Liu
2017-08-01 8:48 ` [PATCH v15 02/23] x86: move cpuid_count_leaf from cpuid.c to processor.h Yi Sun
2017-08-01 8:48 ` [PATCH v15 03/23] x86: refactor psr: remove L3 CAT/CDP codes Yi Sun
2017-08-01 8:48 ` [PATCH v15 04/23] x86: refactor psr: L3 CAT: implement main data structures, CPU init and free flows Yi Sun
2017-08-01 8:48 ` [PATCH v15 05/23] x86: refactor psr: L3 CAT: implement Domain init/free and schedule flows Yi Sun
2017-08-01 8:48 ` [PATCH v15 06/23] x86: refactor psr: L3 CAT: implement get hw info flow Yi Sun
2017-08-01 8:48 ` [PATCH v15 07/23] x86: refactor psr: L3 CAT: implement get value flow Yi Sun
2017-08-01 8:48 ` [PATCH v15 08/23] x86: refactor psr: L3 CAT: set value: implement framework Yi Sun
2017-08-04 3:10 ` [PATCH v15.2 " Yi Sun
2017-08-01 8:48 ` [PATCH v15 09/23] x86: refactor psr: L3 CAT: set value: assemble features value array Yi Sun
2017-08-01 8:48 ` [PATCH v15 10/23] x86: refactor psr: L3 CAT: set value: implement cos finding flow Yi Sun
2017-08-01 8:48 ` [PATCH v15 11/23] x86: refactor psr: L3 CAT: set value: implement cos id picking flow Yi Sun
2017-08-01 8:48 ` [PATCH v15 12/23] x86: refactor psr: L3 CAT: set value: implement write msr flow Yi Sun
2017-08-01 8:48 ` [PATCH v15 13/23] x86: refactor psr: CDP: implement CPU init flow Yi Sun
2017-08-01 9:20 ` Wei Liu
2017-08-02 12:35 ` Jan Beulich
2017-08-02 15:11 ` Yi Sun
2017-08-02 15:19 ` Jan Beulich
2017-08-03 2:10 ` [PATCH v15.1 " Yi Sun
2017-08-03 9:37 ` Jan Beulich
2017-08-04 3:23 ` Yi Sun
2017-08-04 5:42 ` Jan Beulich
2017-08-04 7:42 ` Yi Sun
2017-08-04 3:08 ` [PATCH v15.2 " Yi Sun
2017-08-01 8:48 ` [PATCH v15 14/23] x86: refactor psr: CDP: implement get hw info flow Yi Sun
2017-08-01 8:48 ` [PATCH v15 15/23] x86: refactor psr: CDP: implement set value callback function Yi Sun
2017-08-01 8:48 ` [PATCH v15 16/23] x86: L2 CAT: implement CPU init flow Yi Sun
2017-08-01 8:48 ` [PATCH v15 17/23] x86: L2 CAT: implement get hw info flow Yi Sun
2017-08-01 8:48 ` [PATCH v15 18/23] x86: L2 CAT: implement get value flow Yi Sun
2017-08-01 8:48 ` [PATCH v15 19/23] x86: L2 CAT: implement set " Yi Sun
2017-08-01 8:48 ` [PATCH v15 20/23] tools: L2 CAT: support get HW info for L2 CAT Yi Sun
2017-08-01 8:48 ` [PATCH v15 21/23] tools: L2 CAT: support show cbm " Yi Sun
2017-08-01 8:48 ` [PATCH v15 22/23] tools: L2 CAT: support set " Yi Sun
2017-08-01 8:48 ` [PATCH v15 23/23] docs: add L2 CAT description in docs Yi Sun
2017-08-03 15:37 ` [PATCH v15 00/23] Enable L2 Cache Allocation Technology & Refactor psr.c Andrew Cooper
2017-08-03 22:50 ` Boris Ostrovsky [this message]
2017-08-04 2:21 ` Yi Sun
2017-08-04 4:36 ` Yi Sun
2017-08-04 13:58 ` Yi Sun
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