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keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <1788882453.8631fc262581453bbf619ec5b2062170.1a081b40589000c4f3@vates.tech> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-purgate-ID: tlsNG-bad1c0/1788883086-3A2C4034-22CFF9E1/0/0 X-purgate-type: clean X-purgate-size: 2228 On 08.09.2026 17:47, Baptiste Le Duc wrote: > On 2026-09-08 17:05 +0200, Jan Beulich wrote: >> On 08.09.2026 16:58, Oleksii Kurochko wrote: >>> On 9/8/26 12:01 PM, Oleksii Kurochko wrote: >>>> On 9/7/26 5:57 PM, Baptiste Le Duc wrote: >>>>>> --- a/xen/arch/riscv/include/asm/riscv_encoding.h >>>>>> +++ b/xen/arch/riscv/include/asm/riscv_encoding.h >>>>>> @@ -109,6 +109,12 @@ >>>>>>   #define SIP_SSIP            MIP_SSIP >>>>>>   #define SIP_STIP            MIP_STIP >>>>>> +/* stvec/vstvec: MODE is bits [1:0], BASE is bits [XLEN-1:2] */ >>>>>> +#define STVEC_MODE_MASK            _UL(0x3) >>>>>> +#define STVEC_MODE_DIRECT        _UL(0x0) >>>>>> +#define STVEC_MODE_VECTORED        _UL(0x1) >>>>>> +#define STVEC_BASE_MASK            (~STVEC_MODE_MASK) >>>>> Nit: STVEC_MODE_DIRECT and STVEC_MODE_VECTORED aren't used anywhere in >>>>> this patch (only STVEC_BASE_MASK is). Either use them where you decide >>>>> exceptions always target BASE regardless of MODE, or drop them until a >>>>> patch that needs them. >>>> >>>> IMO it is fine to introduce *_DIRECT/VECORED here as they are used >>>> implicitly through STVEC_BASE_MASK and thereby it will be better to >>>> introduce them here now instead of open-code them and then just update >>>> STVEC_BASE_MASK again when *_DIRECT/VECORED will be re-introduced. >>>> >>> >>> Oh, sorry, you are right. STVEC_MODE_DIRECT and STVEC_MODE_VECTORED are >>> really not used here (in this implementation). I planned to do: >>> >>> #define STVEC_MODE_MASK (STVEC_MODE_DIRECT | STVEC_MODE_VECTORED) >>> >>> But I missed to do in that way. >>> >>> I will update the defintion of STVEC_MODE_MASK in suggested above way. >> >> But that's yield a mask value of 1, when you want it to be 3. That ORing >> together looks bogus to me anyway. >> > Yes I agree. It might be enough, for the moment, to only keep #define > STVEC_MODE_MASK _UL(3) and drop the others defines (even STVEC_BASE_MASK as Jan > mentioned the comment in the caller is already precise enough). To me having STVEC_MODE_MASK without at least one of STVEC_MODE_{DIRECT,VECTORED} would feel odd / incomplete. Jan