xen-devel.lists.xenproject.org archive mirror
 help / color / mirror / Atom feed
From: mjaggi@caviumnetworks.com
To: julien.grall@linaro.org, marc.zyngier@arm.com,
	sstabellini@kernel.org, jgross@suse.com,
	xen-devel@lists.xenproject.org
Cc: manish.jaggi@cavium.com
Subject: [PATCH 00/12] arm64: Mediate access to GICv3 sysregs at EL2
Date: Mon, 12 Mar 2018 18:12:19 +0530	[thread overview]
Message-ID: <cover.1520857428.git.manish.jaggi@cavium.com> (raw)

From: Manish Jaggi <manish.jaggi@cavium.com>

This patchset is a Xen port of Marc's patchset.
arm64: KVM: Mediate access to GICv3 sysregs at EL2 [1]

The current RFC patchset is a subset of [1], as it handleing only Group1 traps
as a PoC. Most of the trap code is added in vsysreg.c. Trap handler function is kept
independent of the usual guest trap handling code. 
Looking for feedback on this approach.  

The errata has been validated on Cavium ThunderX platform.

Steps to reporduce the errata
- Boot Xen with 2 cores.
- Disable group1 interrupts in domU kernel
- start domU, the kill and start again.
One of the Xen core would hang.

Code in this patchset fixes this issue.

[1] https://lists.cs.columbia.edu/pipermail/kvmarm/2017-June/026029.html

Changes from RFC
- Added commit information on ported patches from linux
- Added skip_hyp_tail to control calling leave_hypervisor_tail 
- Added CAVIUM_CONFIG_ERRATUM_30115 which will auto enable workaround

Manish Jaggi (12):
  arm:Kconfig Rename menu text
  arm64: cputype: Add MIDR values for Cavium ThunderX1 CPUs
  arm64: Add config for Cavium Thunder erratum 30115
  Enable Group1 Traps by default for Cavium ThunderX
  Placeholder for handling Group1 register traps
  arm64: vgic-v3: Add ICV_BPR1_EL1 handler
  arm64: vgic-v3: Add ICV_IGRPEN1_EL1 handler
  arm64: Add accessors for the ICH_APxRn_EL2 registers
  Expose ich_read/write_lr in vsysreg_errata.c
  arm64: Add ICV_IAR1_EL1 handler
  arm64: vgic-v3: Add ICV_EOIR1_EL1 handler
  arm64: vgic-v3: Add ICV_HPPIR1_EL1 handler

 xen/arch/arm/Kconfig                |   6 +-
 xen/arch/arm/arm64/Makefile         |   1 +
 xen/arch/arm/arm64/vsysreg_errata.c | 660 ++++++++++++++++++++++++++++++++++++
 xen/arch/arm/cpuerrata.c            |  21 ++
 xen/arch/arm/gic-v3.c               |  16 +-
 xen/arch/arm/traps.c                |  20 ++
 xen/include/asm-arm/arm64/sysregs.h |   5 +
 xen/include/asm-arm/arm64/traps.h   |   3 +-
 xen/include/asm-arm/cpuerrata.h     |   1 +
 xen/include/asm-arm/cpufeature.h    |   3 +-
 xen/include/asm-arm/current.h       |   1 +
 xen/include/asm-arm/gic.h           |   1 +
 xen/include/asm-arm/gic_v3_defs.h   |  29 ++
 xen/include/asm-arm/processor.h     |   9 +
 14 files changed, 771 insertions(+), 5 deletions(-)
 create mode 100644 xen/arch/arm/arm64/vsysreg_errata.c

-- 
2.14.1


_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xenproject.org
https://lists.xenproject.org/mailman/listinfo/xen-devel

             reply	other threads:[~2018-03-12 12:43 UTC|newest]

Thread overview: 23+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-03-12 12:42 mjaggi [this message]
2018-03-12 12:42 ` [PATCH 01/12] arm:Kconfig Rename menu text mjaggi
2018-03-13 12:15   ` Julien Grall
2018-03-15  6:10     ` Manish Jaggi
2018-03-15 11:25       ` Julien Grall
2018-03-12 12:42 ` [PATCH 02/12] arm64: cputype: Add MIDR values for Cavium ThunderX1 CPUs mjaggi
2018-03-13 12:17   ` Julien Grall
2018-03-12 12:42 ` [PATCH 03/12] arm64: Add config for Cavium Thunder erratum 30115 mjaggi
2018-03-13 12:23   ` Julien Grall
2018-03-12 12:42 ` [PATCH 04/12] Enable Group1 Traps by default for Cavium ThunderX1 mjaggi
2018-03-13 12:27   ` Julien Grall
2018-03-12 12:42 ` [PATCH 05/12] Placeholder for handling Group1 register traps mjaggi
2018-03-13 14:30   ` Julien Grall
2018-03-12 12:42 ` [PATCH 06/12] arm64: vgic-v3: Add ICV_BPR1_EL1 handler mjaggi
2018-03-12 12:42 ` [PATCH 07/12] arm64: vgic-v3: Add ICV_IGRPEN1_EL1 handler mjaggi
2018-03-12 12:42 ` [PATCH 08/12] arm64: Add accessors for the ICH_APxRn_EL2 registers mjaggi
2018-03-12 12:42 ` [PATCH 09/12] Expose ich_read/write_lr in vsysreg_errata.c mjaggi
2018-03-13 14:31   ` Julien Grall
2018-03-12 12:42 ` [PATCH 10/12] arm64: Add ICV_IAR1_EL1 handler mjaggi
2018-03-12 12:42 ` [PATCH 11/12] arm64: vgic-v3: Add ICV_EOIR1_EL1 handler mjaggi
2018-03-12 12:42 ` [PATCH 12/12] arm64: vgic-v3: Add ICV_HPPIR1_EL1 handler mjaggi
2018-03-12 12:58 ` [PATCH 00/12] arm64: Mediate access to GICv3 sysregs at EL2 Marc Zyngier
2018-03-13 12:14 ` Julien Grall

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=cover.1520857428.git.manish.jaggi@cavium.com \
    --to=mjaggi@caviumnetworks.com \
    --cc=jgross@suse.com \
    --cc=julien.grall@linaro.org \
    --cc=manish.jaggi@cavium.com \
    --cc=marc.zyngier@arm.com \
    --cc=sstabellini@kernel.org \
    --cc=xen-devel@lists.xenproject.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body. 
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).