[PATCH v1 00/15] arm64: Mediate access to GICv3 sysregs at EL2

From: Manish Jaggi <manish.jaggi@cavium.com>
To: xen-devel@lists.xenproject.org, julien.grall@arm.com,
	sstabellini@kernel.org, marc.zyngier@arm.com,
	andre.przywara@arm.com
Cc: manish.jaggi@cavium.com
Subject: [PATCH v1 00/15] arm64: Mediate access to GICv3 sysregs at EL2
Date: Fri, 16 Mar 2018 17:28:27 +0530	[thread overview]
Message-ID: <cover.1521200294.git.manish.jaggi@cavium.com> (raw)

This patchset is a Xen port of Marc's patchset.
arm64: KVM: Mediate access to GICv3 sysregs at EL2 [1]

The current RFC patchset is a subset of [1], as it handleing only Group1 traps
as a PoC. Most of the trap code is added in vsysreg.c. Trap handler function is kept
independent of the usual guest trap handling code.
Looking for feedback on this approach.

The errata has been validated on Cavium ThunderX platform.

Steps to reporduce the errata
- Boot Xen with 2 cores.
- Disable group1 interrupts in domU kernel
- start domU, the kill and start again.
One of the Xen core would hang.

Code in this patchset fixes this issue.

[1] https://lists.cs.columbia.edu/pipermail/kvmarm/2017-June/026029.html

Changes from v0
- Added Group0 traps.
- Some cleanups and documentation

Changes from RFC
- Added commit information on ported patches from linux
- Added skip_hyp_tail to control calling leave_hypervisor_tail 
- Added CAVIUM_CONFIG_ERRATUM_30115 which will auto enable workaround

Manish Jaggi (15):
  arm64: cputype: Add MIDR values for Cavium ThunderX1 CPU family
  arm64: Add config for Cavium Thunder erratum 30115
  arm: Placeholder for handling Group0/1 traps for Cavium Erratum 30115
  arm64: vgic-v3: Add ICV_BPR1_EL1 handler
  arm64: vgic-v3: Add ICV_IGRPEN1_EL1 handler
  arm64: Add accessors for the ICH_APxRn_EL2 registers
  Expose ich_read/write_lr in vgic-v3-sr.c
  arm64: Add ICV_IAR1_EL1 handler
  arm64: vgic-v3: Add ICV_EOIR1_EL1 handler
  arm64: vgic-v3: Add ICV_HPPIR1_EL1 handler
  arm64: vgic-v3: Add ICV_BPR0_EL1 handler
  arm64: vgic-v3: Add ICV_IGNREN0_EL1 handler
  arm64: vgic-v3: Add misc Group-0 handlers
  arm64: vgic-v3: Add ICV_AP(0/1)Rn_EL1 handler
  Enable Group0/1 Traps by default for Cavium ThunderX1

 docs/misc/arm/silicon-errata.txt    |   1 +
 xen/arch/arm/Kconfig                |  11 +
 xen/arch/arm/arm64/Makefile         |   1 +
 xen/arch/arm/arm64/vgic-v3-sr.c     | 841 ++++++++++++++++++++++++++++++++++++
 xen/arch/arm/cpuerrata.c            |  21 +
 xen/arch/arm/gic-v3.c               |  12 +-
 xen/arch/arm/traps.c                |  31 ++
 xen/include/asm-arm/arm64/sysregs.h |  21 +
 xen/include/asm-arm/arm64/traps.h   |   3 +
 xen/include/asm-arm/cpuerrata.h     |   1 +
 xen/include/asm-arm/cpufeature.h    |   3 +-
 xen/include/asm-arm/current.h       |   3 +-
 xen/include/asm-arm/gic.h           |   2 +
 xen/include/asm-arm/gic_v3_defs.h   |  33 +-
 xen/include/asm-arm/processor.h     |   9 +
 15 files changed, 987 insertions(+), 6 deletions(-)
 create mode 100644 xen/arch/arm/arm64/vgic-v3-sr.c

-- 
2.14.1

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