[PATCH v3 00/17] arm64: Mediate access to GICv3 sysregs at EL2

[Manish Jaggi <mjaggi@caviumnetworks.com>]

This patchset is based on Marc's patchset below.
arm64: KVM: Mediate access to GICv3 sysregs at EL2 [1].

As these patches are ported to Xen specifically for cavium errata 30115
few changes are made:
- Xen coding style is used

- group1_enable / group0_enable command line options not used.
  CONFIG_CAVIUM_ERRATUM_30115 would enable trapping of group0/1 registers

- check_workaround_cavium_30115 function is used instead to check if emulation
  has to be done.

- Not every patch in [1] is ported to xen, ported are ones which are relevant
  to Cavium Errata 30115.

Most of the trap code is added in vgic-v3-sr.c. Trap handler function is kept
independent of the usual guest trap handling code.

Cavium 30115 Errata Workaround:
  Hypervisor to trap and emulate the following registers:
  Group 0: ICC_IAR0_EL1, ICC_EOIR0_EL1, ICC_HPPIR0_EL1, ICC_BPR0_EL1,
           ICC_AP0R0_EL1, ICC_IGRPEN0_EL1
  Group 1: ICC_IAR1_EL1, ICC_EOIR1_EL1, ICC_HPPIR1_EL1, ICC_BPR1_EL1,
           ICC_AP1R0_EL1, ICC_IGRPEN1_EL1

The errata workaround has been validated on Cavium ThunderX1 platform.
Steps to reproduce the errata
- Boot Xen with 2 cores.
- Disable group1 interrupts in domU kernel
- start domU, the kill and start again.
One of the Xen core would hang.

[1] https://www.spinics.net/lists/arm-kernel/msg587082.html

Changes from v2
- remove emulate_XXX functions as per Marc's comment
- Fixed used_lrs in EOIR patch

Changes from v1
- removed __ prefix from function names
- Patches have been realigned to map closely with original patchset

Changes from v0
- Added Group0 traps.
- Some cleanups and documentation

Changes from RFC
- Added commit information on ported patches from linux
- Added skip_hyp_tail to control calling leave_hypervisor_tail 
- Added CAVIUM_CONFIG_ERRATUM_30115 which will auto enable workaround

Manish Jaggi (17):
  arm: Placeholder code to handle guest GICv3 sysreg accesses at EL2
  arm64: vgic-v3: Add ICV_BPR1_EL1 handler
  arm64: vgic-v3: Add ICV_IGRPEN1_EL1 handler
  arm64: vgic-v3: Add accessors for the ICH_APxRn_EL2 registers
  Expose ich_read/write_lr in vgic-v3-sr.c
  arm64: Add ICV_IAR1_EL1 handler
  arm64: vgic-v3: Add ICV_EOIR1_EL1 handler
  arm64: vgic-v3: Add ICV_HPPIR1_EL1 handler
  arm64: vgic-v3: Add ICV_BPR0_EL1 handler
  arm64: vgic-v3: Add ICV_IGRPEN0_EL1 handler
  arm64: vgic-v3: Add ICV_AP1Rn_EL1 handler
  arm64: vgic-v3: Add misc Group-0 handlers
  arm64: cputype: Add MIDR values for Cavium ThunderX1 CPU family
  arm64: Add config for Cavium Thunder erratum 30115
  arm: Hook workaround handler from traps.c based on Cavium
    workaround_30115
  arm64: if trapping a write-to-read-only GICv3 access inject Undef
    exception in guest
  arm64: if trapping a read-from-write-only GICv3 access inject undef
    exception in guest

 docs/misc/arm/silicon-errata.txt    |   1 +
 xen/arch/arm/Kconfig                |  11 +
 xen/arch/arm/arm64/Makefile         |   1 +
 xen/arch/arm/arm64/vgic-v3-sr.c     | 873 ++++++++++++++++++++++++++++++++++++
 xen/arch/arm/cpuerrata.c            |  21 +
 xen/arch/arm/traps.c                |  31 ++
 xen/include/asm-arm/arm64/sysregs.h |  12 +
 xen/include/asm-arm/arm64/traps.h   |   2 +
 xen/include/asm-arm/cpuerrata.h     |   1 +
 xen/include/asm-arm/cpufeature.h    |   3 +-
 xen/include/asm-arm/current.h       |   9 +-
 xen/include/asm-arm/gic.h           |   1 +
 xen/include/asm-arm/gic_v3_defs.h   |  25 ++
 xen/include/asm-arm/processor.h     |   9 +
 14 files changed, 998 insertions(+), 2 deletions(-)
 create mode 100644 xen/arch/arm/arm64/vgic-v3-sr.c

-- 
2.14.1


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