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From: Julien Grall <julien.grall@linaro.org>
To: xen-devel@lists.xen.org
Cc: Marc Zyngier <marc.zyngier@arm.com>,
	sstabellini@kernel.org, andre.przywara@linaro.org
Subject: Re: [PATCH v2 5/7] xen/arm32: Invalidate BTB on guest exit for Cortex A17 and 12
Date: Wed, 31 Jan 2018 17:34:11 +0000	[thread overview]
Message-ID: <d09253ad-a658-92db-4034-c1911a2b7cca@linaro.org> (raw)
In-Reply-To: <20180131165334.23175-6-julien.grall@arm.com>

Hi,

On 31/01/18 16:53, Julien Grall wrote:
> +GLOBAL(hyp_traps_vector_bp_inv)
> +        /*
> +         * We encode the exception entry in the bottom 3 bits of
> +         * SP, and we have to guarantee to be 8 bytes aligned.
> +         */
> +        add sp, sp, #1                  /* Reset            7 */
> +        add sp, sp, #1                  /* Undef            6 */
> +        add sp, sp, #1                  /* Hypervisor Call  5 */
> +        add sp, sp, #1                  /* Prefetch abort   4 */
> +        add sp, sp, #1                  /* Data abort       3 */
> +        add sp, sp, #1                  /* Hypervisor       2 */
> +        add sp, sp, #1                  /* IRQ              1 */
> +        nop                             /* FIQ              0 */
> +
> +        mcr	p15, 0, r0, c7, c5, 6	    /* BPIALL */
> +        isb
> +
> +        /*
> +         * As we cannot use any temporary registers and cannot
> +         * clobber SP, we can decode the exception entry using
> +         * an unrolled binary search.
> +         */
> +        tst sp, #4
> +        bne 1f
> +
> +        tst sp, #2
> +        bne 3f
> +
> +        tst sp, #1
> +        bic sp, sp, #0x7
> +        bne trap_irq
> +        b   trap_fiq
> +
> +1:
> +        tst sp, #2
> +        bne 2f
> +
> +        tst sp, #1
> +        bic sp, sp, #0x7
> +        bne trap_hypervisor_call
> +        b   trap_prefetch_abort
> +
> +2:
> +        tst sp, #1
> +        bic sp, sp, #0x7
> +        bne trap_reset
> +        b   trap_undefined_instruction
> +
> +3:
> +        tst sp, #1
> +        bic sp, sp, #0x7
> +        bne trap_data_abort
> +        b   trap_guest_sync

Just after I hit the sent button Marc pointed me to a discussion on 
Linux ML [1].

They found a solution which would streamline the code, improve the 
readability and prioritize exception.

I would be tempt to use a similar solution on Xen. Stefano, do you have 
any opinions? Shall I respin the series or do a follow-up?

Cheers,

-- 
Julien Grall

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  reply	other threads:[~2018-01-31 17:34 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-01-31 16:53 [PATCH v2 0/7] xen/arm32: Branch predictor hardening (XSA-254 variant 2) Julien Grall
2018-01-31 16:53 ` [PATCH v2 1/7] xen/arm32: entry: Consolidate DEFINE_TRAP_ENTRY_* macros Julien Grall
2018-01-31 16:53 ` [PATCH v2 2/7] xen/arm32: Add missing MIDR values for Cortex-A17 and A12 Julien Grall
2018-01-31 16:53 ` [PATCH v2 3/7] xen/arm32: entry: Add missing trap_reset entry Julien Grall
2018-01-31 17:29   ` Stefano Stabellini
2018-01-31 16:53 ` [PATCH v2 4/7] xen/arm32: Add skeleton to harden branch predictor aliasing attacks Julien Grall
2018-01-31 17:30   ` Stefano Stabellini
2018-01-31 16:53 ` [PATCH v2 5/7] xen/arm32: Invalidate BTB on guest exit for Cortex A17 and 12 Julien Grall
2018-01-31 17:34   ` Julien Grall [this message]
2018-01-31 17:39     ` Stefano Stabellini
2018-01-31 17:39       ` Julien Grall
2018-01-31 16:53 ` [PATCH v2 6/7] xen/arm32: Invalidate icache on guest exist for Cortex-A15 Julien Grall
2018-01-31 16:53 ` [PATCH v2 7/7] xen/arm32: entry: Document the purpose of r11 in the traps handler Julien Grall

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