From: Paul Durrant <Paul.Durrant@citrix.com>
To: 'Jan Beulich' <JBeulich@suse.com>
Cc: "xen-devel@lists.xenproject.org" <xen-devel@lists.xenproject.org>
Subject: Re: [PATCH v2] x86/hvm: fix interaction between internal and external emulation
Date: Tue, 5 Dec 2017 14:37:55 +0000 [thread overview]
Message-ID: <d1218d36856b44368a9c8ee328ecd9a1@AMSPEX02CL03.citrite.net> (raw)
In-Reply-To: <5A26BBF80200007800194BE1@prv-mh.provo.novell.com>
> -----Original Message-----
> From: Jan Beulich [mailto:JBeulich@suse.com]
> Sent: 05 December 2017 14:32
> To: Paul Durrant <Paul.Durrant@citrix.com>
> Cc: xen-devel@lists.xenproject.org
> Subject: RE: [PATCH v2] x86/hvm: fix interaction between internal and
> external emulation
>
> >>> On 05.12.17 at 15:00, <Paul.Durrant@citrix.com> wrote:
> >> From: Jan Beulich [mailto:JBeulich@suse.com]
> >> Sent: 05 December 2017 13:53
> >> >>> On 28.11.17 at 15:05, <paul.durrant@citrix.com> wrote:
> >> rc = x86_emulate(&hvmemul_ctxt->ctxt, ops);
> >>
> >> if ( rc != X86EMUL_RETRY )
> >> {
> >> vio->mmio_cache_count = 0;
> >> vio->mmio_insn_bytes = 0;
> >> }
> >> else
> >> {
> >> ...
> >> }
> >> if ( rc == X86EMUL_OKAY && vio->mmio_retry )
> >> rc = X86EMUL_RETRY;
> >>
> >
> > But that's not safe is it? If we've only completed some of the reps of an
> > instruction then we can't flush the instruction cache and we can't allow the
> > guest to take interrupts, can we?
>
> Of course we can, just like a repeated string insn may be
> interrupted on bare hardware between any two iterations (with
> RIP still pointing at that insn). In fact with EFLAGS.TF set it is a
> requirement to deliver #DB after every iteration.
Ok. In that case your re-ordering would seem sound.
Paul
>
> Jan
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prev parent reply other threads:[~2017-12-05 14:38 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-11-28 14:05 [PATCH v2] x86/hvm: fix interaction between internal and external emulation Paul Durrant
2017-11-30 14:28 ` Jan Beulich
2017-12-01 16:14 ` Julien Grall
2017-12-01 16:55 ` Jan Beulich
2017-12-01 17:59 ` Andrew Cooper
2017-12-05 13:52 ` Jan Beulich
2017-12-05 14:00 ` Paul Durrant
2017-12-05 14:11 ` Paul Durrant
2017-12-05 14:35 ` Jan Beulich
2017-12-05 14:32 ` Jan Beulich
2017-12-05 14:37 ` Paul Durrant [this message]
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