Re: [PATCH v2 13/45] ARM: vPL011: Use the VGIC's level triggered IRQs handling if available

[Julien Grall <julien.grall@arm.com>]

Hi Andre,

On 03/15/2018 08:30 PM, Andre Przywara wrote:
> The emulated ARM SBSA UART is using level triggered IRQ semantics,
> however the current VGIC can only handle edge triggered IRQs, really.
> Disable the existing workaround for this problem in case we have the
> new VGIC in place, which can properly handle level triggered IRQs.
> 
> Signed-off-by: Andre Przywara <andre.przywara@linaro.org>

Reviewed-by: Julien Grall <julien.grall@arm.com>

Cheers,

> ---
> Changelog v1 ... v2:
> - remove unneeded "!!"
> 
>   xen/arch/arm/vpl011.c | 4 ++++
>   1 file changed, 4 insertions(+)
> 
> diff --git a/xen/arch/arm/vpl011.c b/xen/arch/arm/vpl011.c
> index 5dcf4bec18..a281eabd7e 100644
> --- a/xen/arch/arm/vpl011.c
> +++ b/xen/arch/arm/vpl011.c
> @@ -54,6 +54,7 @@ static void vpl011_update_interrupt_status(struct domain *d)
>        */
>       ASSERT(spin_is_locked(&vpl011->lock));
>   
> +#ifndef CONFIG_NEW_VGIC
>       /*
>        * TODO: PL011 interrupts are level triggered which means
>        * that interrupt needs to be set/clear instead of being
> @@ -71,6 +72,9 @@ static void vpl011_update_interrupt_status(struct domain *d)
>           vgic_inject_irq(d, NULL, GUEST_VPL011_SPI, true);
>   
>       vpl011->shadow_uartmis = uartmis;
> +#else
> +    vgic_inject_irq(d, NULL, GUEST_VPL011_SPI, uartmis);
> +#endif
>   }
>   
>   static uint8_t vpl011_read_data(struct domain *d)
> 

-- 
Julien Grall

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