From: Julien Grall <julien.grall@linaro.org>
To: mjaggi@caviumnetworks.com, marc.zyngier@arm.com,
sstabellini@kernel.org, jgross@suse.com,
xen-devel@lists.xenproject.org
Cc: manish.jaggi@cavium.com
Subject: Re: [PATCH 01/12] arm:Kconfig Rename menu text
Date: Tue, 13 Mar 2018 12:15:46 +0000 [thread overview]
Message-ID: <d4550836-f63d-eea4-30d9-d2fd505e7c08@linaro.org> (raw)
In-Reply-To: <8f00c7bf93c9d0d66fb6ed70cc2f5bf0dbb5e7ab.1520857428.git.manish.jaggi@cavium.com>
Hi,
On 12/03/18 12:42, mjaggi@caviumnetworks.com wrote:
> From: Manish Jaggi <manish.jaggi@cavium.com>
>
> Rename the menu text to Errata Workarounds. Subsequent patches will
> add config options for SoC specific erratas.
Well, your SoC is an Arm SoC, right? So what is the benefits of this new
name? More that it still depends on HAS_ALTERNATIVE.
Cheers,
>
> Signed-off-by: Manish Jaggi <manish.jaggi@cavium.com>
> ---
> xen/arch/arm/Kconfig | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/xen/arch/arm/Kconfig b/xen/arch/arm/Kconfig
> index f58019d6ed..10a6d1a956 100644
> --- a/xen/arch/arm/Kconfig
> +++ b/xen/arch/arm/Kconfig
> @@ -59,7 +59,7 @@ config SBSA_VUART_CONSOLE
>
> endmenu
>
> -menu "ARM errata workaround via the alternative framework"
> +menu "Errata workarounds"
> depends on HAS_ALTERNATIVE >
> config ARM64_ERRATUM_827319
>
--
Julien Grall
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next prev parent reply other threads:[~2018-03-13 12:15 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-03-12 12:42 [PATCH 00/12] arm64: Mediate access to GICv3 sysregs at EL2 mjaggi
2018-03-12 12:42 ` [PATCH 01/12] arm:Kconfig Rename menu text mjaggi
2018-03-13 12:15 ` Julien Grall [this message]
2018-03-15 6:10 ` Manish Jaggi
2018-03-15 11:25 ` Julien Grall
2018-03-12 12:42 ` [PATCH 02/12] arm64: cputype: Add MIDR values for Cavium ThunderX1 CPUs mjaggi
2018-03-13 12:17 ` Julien Grall
2018-03-12 12:42 ` [PATCH 03/12] arm64: Add config for Cavium Thunder erratum 30115 mjaggi
2018-03-13 12:23 ` Julien Grall
2018-03-12 12:42 ` [PATCH 04/12] Enable Group1 Traps by default for Cavium ThunderX1 mjaggi
2018-03-13 12:27 ` Julien Grall
2018-03-12 12:42 ` [PATCH 05/12] Placeholder for handling Group1 register traps mjaggi
2018-03-13 14:30 ` Julien Grall
2018-03-12 12:42 ` [PATCH 06/12] arm64: vgic-v3: Add ICV_BPR1_EL1 handler mjaggi
2018-03-12 12:42 ` [PATCH 07/12] arm64: vgic-v3: Add ICV_IGRPEN1_EL1 handler mjaggi
2018-03-12 12:42 ` [PATCH 08/12] arm64: Add accessors for the ICH_APxRn_EL2 registers mjaggi
2018-03-12 12:42 ` [PATCH 09/12] Expose ich_read/write_lr in vsysreg_errata.c mjaggi
2018-03-13 14:31 ` Julien Grall
2018-03-12 12:42 ` [PATCH 10/12] arm64: Add ICV_IAR1_EL1 handler mjaggi
2018-03-12 12:42 ` [PATCH 11/12] arm64: vgic-v3: Add ICV_EOIR1_EL1 handler mjaggi
2018-03-12 12:42 ` [PATCH 12/12] arm64: vgic-v3: Add ICV_HPPIR1_EL1 handler mjaggi
2018-03-12 12:58 ` [PATCH 00/12] arm64: Mediate access to GICv3 sysregs at EL2 Marc Zyngier
2018-03-13 12:14 ` Julien Grall
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