From: Julien Grall <julien.grall@linaro.org>
To: mjaggi@caviumnetworks.com, marc.zyngier@arm.com,
sstabellini@kernel.org, jgross@suse.com,
xen-devel@lists.xenproject.org
Cc: manish.jaggi@cavium.com
Subject: Re: [PATCH 09/12] Expose ich_read/write_lr in vsysreg_errata.c
Date: Tue, 13 Mar 2018 14:31:28 +0000 [thread overview]
Message-ID: <e02596bd-1482-f12f-857e-8a0a437ccfbf@linaro.org> (raw)
In-Reply-To: <6b3c06fd9729a66b4f7582e9b6afba4c4c3ff91d.1520857428.git.manish.jaggi@cavium.com>
On 12/03/18 12:42, mjaggi@caviumnetworks.com wrote:
> From: Manish Jaggi <manish.jaggi@cavium.com>
>
> gicv3_ich_read/write_lr functions are duplicated in vsysreg_errata.c
Please explain the rationale. I.e we want to have the workaround standalone.
Cheers,
>
> Signed-off-by: Manish Jaggi <manish.jaggi@cavium.com>
> ---
> xen/arch/arm/arm64/vsysreg_errata.c | 83 +++++++++++++++++++++++++++++++++++++
> 1 file changed, 83 insertions(+)
>
> diff --git a/xen/arch/arm/arm64/vsysreg_errata.c b/xen/arch/arm/arm64/vsysreg_errata.c
> index b2a95a69dc..d7bf9d6ce3 100644
> --- a/xen/arch/arm/arm64/vsysreg_errata.c
> +++ b/xen/arch/arm/arm64/vsysreg_errata.c
> @@ -189,6 +189,89 @@ u32 __vgic_v3_read_ap1rn(int n)
> return val;
> }
>
> +static uint64_t gicv3_ich_read_lr(int lr)
> +{
> + switch ( lr )
> + {
> + case 0: return READ_SYSREG(ICH_LR0_EL2);
> + case 1: return READ_SYSREG(ICH_LR1_EL2);
> + case 2: return READ_SYSREG(ICH_LR2_EL2);
> + case 3: return READ_SYSREG(ICH_LR3_EL2);
> + case 4: return READ_SYSREG(ICH_LR4_EL2);
> + case 5: return READ_SYSREG(ICH_LR5_EL2);
> + case 6: return READ_SYSREG(ICH_LR6_EL2);
> + case 7: return READ_SYSREG(ICH_LR7_EL2);
> + case 8: return READ_SYSREG(ICH_LR8_EL2);
> + case 9: return READ_SYSREG(ICH_LR9_EL2);
> + case 10: return READ_SYSREG(ICH_LR10_EL2);
> + case 11: return READ_SYSREG(ICH_LR11_EL2);
> + case 12: return READ_SYSREG(ICH_LR12_EL2);
> + case 13: return READ_SYSREG(ICH_LR13_EL2);
> + case 14: return READ_SYSREG(ICH_LR14_EL2);
> + case 15: return READ_SYSREG(ICH_LR15_EL2);
> + default:
> + BUG();
> + }
> +}
> +
> +static void gicv3_ich_write_lr(int lr, uint64_t val)
> +{
> + switch ( lr )
> + {
> + case 0:
> + WRITE_SYSREG(val, ICH_LR0_EL2);
> + break;
> + case 1:
> + WRITE_SYSREG(val, ICH_LR1_EL2);
> + break;
> + case 2:
> + WRITE_SYSREG(val, ICH_LR2_EL2);
> + break;
> + case 3:
> + WRITE_SYSREG(val, ICH_LR3_EL2);
> + break;
> + case 4:
> + WRITE_SYSREG(val, ICH_LR4_EL2);
> + break;
> + case 5:
> + WRITE_SYSREG(val, ICH_LR5_EL2);
> + break;
> + case 6:
> + WRITE_SYSREG(val, ICH_LR6_EL2);
> + break;
> + case 7:
> + WRITE_SYSREG(val, ICH_LR7_EL2);
> + break;
> + case 8:
> + WRITE_SYSREG(val, ICH_LR8_EL2);
> + break;
> + case 9:
> + WRITE_SYSREG(val, ICH_LR9_EL2);
> + break;
> + case 10:
> + WRITE_SYSREG(val, ICH_LR10_EL2);
> + break;
> + case 11:
> + WRITE_SYSREG(val, ICH_LR11_EL2);
> + break;
> + case 12:
> + WRITE_SYSREG(val, ICH_LR12_EL2);
> + break;
> + case 13:
> + WRITE_SYSREG(val, ICH_LR13_EL2);
> + break;
> + case 14:
> + WRITE_SYSREG(val, ICH_LR14_EL2);
> + break;
> + case 15:
> + WRITE_SYSREG(val, ICH_LR15_EL2);
> + break;
> + default:
> + return;
> + }
> + isb();
> +}
> +
> bool vgic_v3_handle_cpuif_access(struct cpu_user_regs *regs, const union hsr hsr)
> {
> bool ret = 0;
>
--
Julien Grall
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next prev parent reply other threads:[~2018-03-13 14:31 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-03-12 12:42 [PATCH 00/12] arm64: Mediate access to GICv3 sysregs at EL2 mjaggi
2018-03-12 12:42 ` [PATCH 01/12] arm:Kconfig Rename menu text mjaggi
2018-03-13 12:15 ` Julien Grall
2018-03-15 6:10 ` Manish Jaggi
2018-03-15 11:25 ` Julien Grall
2018-03-12 12:42 ` [PATCH 02/12] arm64: cputype: Add MIDR values for Cavium ThunderX1 CPUs mjaggi
2018-03-13 12:17 ` Julien Grall
2018-03-12 12:42 ` [PATCH 03/12] arm64: Add config for Cavium Thunder erratum 30115 mjaggi
2018-03-13 12:23 ` Julien Grall
2018-03-12 12:42 ` [PATCH 04/12] Enable Group1 Traps by default for Cavium ThunderX1 mjaggi
2018-03-13 12:27 ` Julien Grall
2018-03-12 12:42 ` [PATCH 05/12] Placeholder for handling Group1 register traps mjaggi
2018-03-13 14:30 ` Julien Grall
2018-03-12 12:42 ` [PATCH 06/12] arm64: vgic-v3: Add ICV_BPR1_EL1 handler mjaggi
2018-03-12 12:42 ` [PATCH 07/12] arm64: vgic-v3: Add ICV_IGRPEN1_EL1 handler mjaggi
2018-03-12 12:42 ` [PATCH 08/12] arm64: Add accessors for the ICH_APxRn_EL2 registers mjaggi
2018-03-12 12:42 ` [PATCH 09/12] Expose ich_read/write_lr in vsysreg_errata.c mjaggi
2018-03-13 14:31 ` Julien Grall [this message]
2018-03-12 12:42 ` [PATCH 10/12] arm64: Add ICV_IAR1_EL1 handler mjaggi
2018-03-12 12:42 ` [PATCH 11/12] arm64: vgic-v3: Add ICV_EOIR1_EL1 handler mjaggi
2018-03-12 12:42 ` [PATCH 12/12] arm64: vgic-v3: Add ICV_HPPIR1_EL1 handler mjaggi
2018-03-12 12:58 ` [PATCH 00/12] arm64: Mediate access to GICv3 sysregs at EL2 Marc Zyngier
2018-03-13 12:14 ` Julien Grall
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