From: Julien Grall <julien.grall@arm.com>
To: Andre Przywara <andre.przywara@arm.com>,
Stefano Stabellini <sstabellini@kernel.org>
Cc: xen-devel@lists.xenproject.org,
Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com>,
Vijay Kilari <vijay.kilari@gmail.com>,
Shanker Donthineni <shankerd@codeaurora.org>
Subject: Re: [PATCH v8 23/27] ARM: vITS: handle INV command
Date: Thu, 11 May 2017 11:43:27 +0100 [thread overview]
Message-ID: <e2ecebd1-ef8e-d29a-3075-32b8d12c459c@arm.com> (raw)
In-Reply-To: <a38c71fe-81fa-f510-f7b8-be8279fc2027@arm.com>
On 10/05/17 16:11, Andre Przywara wrote:
> Hi,
Hi Andre,
> On 12/04/17 18:20, Julien Grall wrote:
>> On 12/04/17 01:44, Andre Przywara wrote:
>>
>>> +{
>>> + ASSERT(spin_is_locked(&v->arch.vgic.lock));
>>
>> The locking is likely to wrong here too (see patch #2). For instance
>> with a MOVI then INV on interrupt enabled.
>>
>>> +
>>> + if ( test_bit(GIC_IRQ_GUEST_ENABLED, &p->status) )
>>> + {
>>> + if ( !list_empty(&p->inflight) &&
>>> + !test_bit(GIC_IRQ_GUEST_VISIBLE, &p->status) )
>>> + gic_raise_guest_irq(v, vlpi, p->lpi_priority);
>>> + }
>>> + else
>>> + {
>>> + clear_bit(GIC_IRQ_GUEST_ENABLED, &p->status);
>>> + list_del_init(&p->lr_queue);
>>> + }
>>> +}
>>> +
>>> +static int its_handle_inv(struct virt_its *its, uint64_t *cmdptr)
>>> +{
>>> + struct domain *d = its->d;
>>> + uint32_t devid = its_cmd_get_deviceid(cmdptr);
>>> + uint32_t eventid = its_cmd_get_id(cmdptr);
>>> + struct pending_irq *p;
>>> + unsigned long flags;
>>> + struct vcpu *vcpu;
>>> + uint32_t vlpi;
>>> + int ret = -1;
>>> +
>>> + /* Translate the event into a vCPU/vLPI pair. */
>>> + if ( !read_itte(its, devid, eventid, &vcpu, &vlpi) )
>>> + return -1;
>>> +
>>> + if ( vlpi == INVALID_LPI )
>>> + return -1;
>>> +
>>> + spin_lock_irqsave(&vcpu->arch.vgic.lock, flags);
>>> +
>>> + p = d->arch.vgic.handler->lpi_to_pending(d, vlpi);
>>> + if ( !p )
>>> + goto out_unlock;
>>
>> As said on v5, this could be simpler and use the pending_irqs in the
>> device. That would be an improvement though. So a would be good.
>
> Originally I found it more straight-forward to use the one existing
> interface (the rbtree) we also use in the VGIC part, which would allow
> us to handle locking or ref-counting in one central place.
> But indeed the ITS command handling has all the data we need to find the
> pending_irq directly from the virtual device.
> So I replaced all lpi_to_pending() calls in those handlers with a new
> function gicv3_its_get_event_pending_irq(), which looks up the struct
> from an ITS/device/event triple.
> I take and keep the its->lock for the runtime of these functions, so
> those events and their memory will not vanish meanwhile.
>
> Does that make sense?
It makes sense to keep the ref-counting in one central place. But it is
better to avoid reading guest memory and therefore avoid most of
checking and overhead to translate the IPA to PA.
That's why I suggested to use pending_irqs :).
Cheers,
--
Julien Grall
_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xen.org
https://lists.xen.org/xen-devel
next prev parent reply other threads:[~2017-05-11 10:43 UTC|newest]
Thread overview: 82+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-04-12 0:44 [PATCH v8 00/27] arm64: Dom0 ITS emulation Andre Przywara
2017-04-12 0:44 ` [PATCH v8 01/27] ARM: GICv3: propagate number of host LPIs to GICv3 guest Andre Przywara
2017-04-12 10:06 ` Julien Grall
2017-04-12 0:44 ` [PATCH v8 02/27] ARM: VGIC: move irq_to_pending() calls under the VGIC VCPU lock Andre Przywara
2017-04-12 10:13 ` Julien Grall
2017-04-12 11:38 ` Julien Grall
2017-04-12 0:44 ` [PATCH v8 03/27] ARM: GIC: Add checks for NULL pointer pending_irq's Andre Przywara
2017-04-12 10:25 ` Julien Grall
2017-04-12 14:51 ` Andre Przywara
2017-04-12 14:52 ` Julien Grall
2017-04-12 0:44 ` [PATCH v8 04/27] ARM: GICv3: introduce separate pending_irq structs for LPIs Andre Przywara
2017-04-12 10:35 ` Julien Grall
2017-04-12 0:44 ` [PATCH v8 05/27] ARM: GICv3: forward pending LPIs to guests Andre Przywara
2017-04-12 10:44 ` Julien Grall
2017-04-12 17:26 ` Andre Przywara
2017-05-10 10:47 ` Andre Przywara
2017-05-10 11:07 ` Julien Grall
2017-05-10 17:14 ` Andre Przywara
2017-05-10 17:17 ` Julien Grall
2017-05-11 17:55 ` Andre Przywara
2017-04-12 0:44 ` [PATCH v8 06/27] ARM: GICv3: enable ITS and LPIs on the host Andre Przywara
2017-04-12 0:44 ` [PATCH v8 07/27] ARM: vGICv3: handle virtual LPI pending and property tables Andre Przywara
2017-04-12 10:55 ` Julien Grall
2017-04-12 13:12 ` Andre Przywara
2017-04-12 13:13 ` Julien Grall
2017-05-11 17:54 ` Andre Przywara
2017-04-12 0:44 ` [PATCH v8 08/27] ARM: introduce vgic_access_guest_memory() Andre Przywara
2017-04-12 12:29 ` Julien Grall
2017-04-12 0:44 ` [PATCH v8 09/27] ARM: vGICv3: re-use vgic_reg64_check_access Andre Przywara
2017-04-12 0:44 ` [PATCH v8 10/27] ARM: GIC: export vgic_init_pending_irq() Andre Przywara
2017-04-12 0:44 ` [PATCH v8 11/27] ARM: VGIC: add vcpu_id to struct pending_irq Andre Przywara
2017-04-12 12:32 ` Julien Grall
2017-04-12 12:37 ` Andre Przywara
2017-04-12 0:44 ` [PATCH v8 12/27] ARM: vGIC: advertise LPI support Andre Przywara
2017-04-12 12:38 ` Julien Grall
2017-04-12 12:48 ` Andre Przywara
2017-04-12 13:04 ` Julien Grall
2017-04-12 0:44 ` [PATCH v8 13/27] ARM: vITS: add command handling stub and MMIO emulation Andre Przywara
2017-04-12 12:59 ` Julien Grall
2017-04-12 0:44 ` [PATCH v8 14/27] ARM: vITS: introduce translation table walks Andre Przywara
2017-04-12 13:22 ` Julien Grall
2017-04-12 13:36 ` Andre Przywara
2017-04-12 13:37 ` Julien Grall
2017-04-12 0:44 ` [PATCH v8 15/27] ARM: vITS: handle CLEAR command Andre Przywara
2017-04-12 14:10 ` Julien Grall
2017-04-12 14:29 ` Andre Przywara
2017-04-12 14:49 ` Julien Grall
2017-04-12 0:44 ` [PATCH v8 16/27] ARM: vITS: handle INT command Andre Przywara
2017-04-12 14:50 ` Julien Grall
2017-04-12 0:44 ` [PATCH v8 17/27] ARM: vITS: handle MAPC command Andre Przywara
2017-04-12 14:51 ` Julien Grall
2017-04-12 0:44 ` [PATCH v8 18/27] ARM: vITS: handle MAPD command Andre Przywara
2017-04-12 15:21 ` Julien Grall
2017-04-12 17:03 ` Andre Przywara
2017-04-12 17:05 ` Julien Grall
2017-04-12 17:24 ` Andrew Cooper
2017-04-12 18:18 ` Wei Liu
2017-05-10 10:42 ` Andre Przywara
2017-05-10 11:30 ` Julien Grall
2017-04-12 0:44 ` [PATCH v8 19/27] ARM: vITS: handle MAPTI command Andre Przywara
2017-04-12 16:18 ` Julien Grall
2017-04-12 16:27 ` Andre Przywara
2017-04-12 17:16 ` Julien Grall
2017-04-12 17:25 ` Julien Grall
2017-04-12 0:44 ` [PATCH v8 20/27] ARM: GICv3: handle unmapped LPIs Andre Przywara
2017-04-12 9:46 ` Andre Przywara
2017-04-12 16:49 ` Julien Grall
2017-04-12 0:44 ` [PATCH v8 21/27] ARM: vITS: handle MOVI command Andre Przywara
2017-04-12 16:59 ` Julien Grall
2017-05-10 10:34 ` Andre Przywara
2017-04-12 0:44 ` [PATCH v8 22/27] ARM: vITS: handle DISCARD command Andre Przywara
2017-04-12 17:06 ` Julien Grall
2017-04-12 0:44 ` [PATCH v8 23/27] ARM: vITS: handle INV command Andre Przywara
2017-04-12 17:20 ` Julien Grall
2017-05-10 15:11 ` Andre Przywara
2017-05-11 10:43 ` Julien Grall [this message]
2017-04-12 0:44 ` [PATCH v8 24/27] ARM: vITS: handle INVALL command Andre Przywara
2017-04-12 17:26 ` Julien Grall
2017-04-12 0:44 ` [PATCH v8 25/27] ARM: vITS: increase mmio_count for each ITS Andre Przywara
2017-04-12 0:44 ` [PATCH v8 26/27] ARM: vITS: create and initialize virtual ITSes for Dom0 Andre Przywara
2017-04-12 0:44 ` [PATCH v8 27/27] ARM: vITS: create ITS subnodes for Dom0 DT Andre Przywara
2017-04-12 14:13 ` [PATCH v8 00/27] arm64: Dom0 ITS emulation Julien Grall
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=e2ecebd1-ef8e-d29a-3075-32b8d12c459c@arm.com \
--to=julien.grall@arm.com \
--cc=Vijaya.Kumar@caviumnetworks.com \
--cc=andre.przywara@arm.com \
--cc=shankerd@codeaurora.org \
--cc=sstabellini@kernel.org \
--cc=vijay.kilari@gmail.com \
--cc=xen-devel@lists.xenproject.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).