From: Andres Lagar-Cavilla <andres@lagarcavilla.org>
To: xen-devel@lists.xen.org
Cc: olaf@aepfle.de, keir@xen.org, andres@gridcentric.ca, tim@xen.org,
wei.wang2@amd.com, hongkaixing@huawei.com, adin@gridcentric.ca
Subject: [PATCH 2 of 3] Clip mfn to allowable width when building a PTE
Date: Wed, 21 Mar 2012 15:22:59 -0400 [thread overview]
Message-ID: <e325da6633453f081303.1332357779@xdev.gridcentric.ca> (raw)
In-Reply-To: <patchbomb.1332357777@xdev.gridcentric.ca>
xen/include/asm-x86/page.h | 12 ++++++++----
1 files changed, 8 insertions(+), 4 deletions(-)
Otherwise, INVALID_MFN tramples over high order bits used for additional flags.
Signed-off-by: Andres Lagar-Cavilla <andres@lagarcavilla.org>
Signed-off-by: Tim Deegan <tim@xen.org>
diff -r 642c0e6a01c2 -r e325da663345 xen/include/asm-x86/page.h
--- a/xen/include/asm-x86/page.h
+++ b/xen/include/asm-x86/page.h
@@ -107,13 +107,17 @@
/* Construct a pte from a pfn and access flags. */
#define l1e_from_pfn(pfn, flags) \
- ((l1_pgentry_t) { ((intpte_t)(pfn) << PAGE_SHIFT) | put_pte_flags(flags) })
+ ((l1_pgentry_t) { (((intpte_t)(pfn) << PAGE_SHIFT) & PADDR_MASK) \
+ | put_pte_flags(flags) })
#define l2e_from_pfn(pfn, flags) \
- ((l2_pgentry_t) { ((intpte_t)(pfn) << PAGE_SHIFT) | put_pte_flags(flags) })
+ ((l2_pgentry_t) { (((intpte_t)(pfn) << PAGE_SHIFT) & PADDR_MASK) \
+ | put_pte_flags(flags) })
#define l3e_from_pfn(pfn, flags) \
- ((l3_pgentry_t) { ((intpte_t)(pfn) << PAGE_SHIFT) | put_pte_flags(flags) })
+ ((l3_pgentry_t) { (((intpte_t)(pfn) << PAGE_SHIFT) & PADDR_MASK) \
+ | put_pte_flags(flags) })
#define l4e_from_pfn(pfn, flags) \
- ((l4_pgentry_t) { ((intpte_t)(pfn) << PAGE_SHIFT) | put_pte_flags(flags) })
+ ((l4_pgentry_t) { (((intpte_t)(pfn) << PAGE_SHIFT) & PADDR_MASK) \
+ | put_pte_flags(flags) })
/* Construct a pte from a physical address and access flags. */
#ifndef __ASSEMBLY__
next prev parent reply other threads:[~2012-03-21 19:22 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-03-21 19:22 [PATCH 0 of 3] Fixes for paging/sharing with AMD processors Andres Lagar-Cavilla
2012-03-21 19:22 ` [PATCH 1 of 3] IOMMU: Add command line param to disable sharing of IOMMU and hap tables Andres Lagar-Cavilla
2012-03-22 9:17 ` Jan Beulich
2012-03-22 10:44 ` Tim Deegan
2012-03-22 10:57 ` Jan Beulich
2012-03-22 11:03 ` Tim Deegan
2012-03-27 15:19 ` Andres Lagar-Cavilla
2012-03-29 10:27 ` Tim Deegan
2012-03-29 10:57 ` Keir Fraser
2012-03-29 11:09 ` Tim Deegan
2012-03-29 15:05 ` Jan Beulich
2012-03-21 19:22 ` Andres Lagar-Cavilla [this message]
2012-03-22 9:18 ` [PATCH 2 of 3] Clip mfn to allowable width when building a PTE Jan Beulich
2012-03-22 10:50 ` Tim Deegan
2012-03-22 11:02 ` Jan Beulich
2012-03-22 14:54 ` Andres Lagar-Cavilla
2012-03-22 15:31 ` Jan Beulich
2012-03-27 15:21 ` Andres Lagar-Cavilla
2012-03-21 19:23 ` [PATCH 3 of 3] x86/mm: Teach paging to page table-based p2m Andres Lagar-Cavilla
2012-03-22 10:55 ` Tim Deegan
2012-03-22 14:47 ` Andres Lagar-Cavilla
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