From mboxrd@z Thu Jan 1 00:00:00 1970 From: Boris Ostrovsky Subject: Re: [PATCH v2] x86/vpmu_intel: Fix hypervisor crash by masking PC bit in MSR_P6_EVNTSEL Date: Thu, 27 Apr 2017 10:57:38 -0400 Message-ID: References: <20170426181104.10112-1-mohit.gambhir@oracle.com> <35183ca6-379e-6605-e5ed-6f54ee2e6639@citrix.com> <23427c77-0b2b-0046-13dc-6a3dddfe85a1@oracle.com> <5901BABA0200007800154A59@prv-mh.provo.novell.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: In-Reply-To: <5901BABA0200007800154A59@prv-mh.provo.novell.com> List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" To: Jan Beulich , Mohit Gambhir Cc: Andrew Cooper , kevin.tian@intel.com, jun.nakajima@intel.com, xen-devel@lists.xen.org List-Id: xen-devel@lists.xenproject.org T24gMDQvMjcvMjAxNyAwMzozMiBBTSwgSmFuIEJldWxpY2ggd3JvdGU6Cj4+Pj4gT24gMjYuMDQu MTcgYXQgMjA6NTAsIDxtb2hpdC5nYW1iaGlyQG9yYWNsZS5jb20+IHdyb3RlOgo+PiBPbiAwNC8y Ni8yMDE3IDAyOjE5IFBNLCBBbmRyZXcgQ29vcGVyIHdyb3RlOgo+Pj4gT24gMjYvMDQvMTcgMTk6 MTEsIE1vaGl0IEdhbWJoaXIgd3JvdGU6Cj4+Pj4gU2V0dGluZyBQaW4gQ29udHJvbCAoUEMpIGJp dCAoMTkpIGluIE1TUl9QNl9FVk5UU0VMIHJlc3VsdHMgaW4gYSBHZW5lcmFsCj4+Pj4gUHJvdGVj dGlvbiBGYXVsdCBhbmQgdGh1cyByZXN1bHRzIGluIGEgaHlwZXJ2aXNvciBjcmFzaC4gVGhpcyBw YXRjaCBmaXhlcyB0aGUKPj4+PiBjcmFzaCBieSBtYXNraW5nIFBDIGJpdCBhbmQgcmV0dXJuaW5n IGFuIGVycm9yIGluIGNhc2UgYW55IGd1ZXN0IHRyaWVzIHRvIHdyaXRlCj4+Pj4gdG8gaXQuCj4+ Pj4KPj4+PiBTaWduZWQtb2ZmLWJ5OiBNb2hpdCBHYW1iaGlyIDxtb2hpdC5nYW1iaGlyQG9yYWNs ZS5jb20+Cj4+PiBPdXQgb2YgaW50ZXJlc3QsIHdoaWNoIGhhcmR3YXJlIGhhcyB0aGlzIGJlZW4g b2JzZXJ2ZWQgb24/Cj4+IEkgaGF2ZSB0ZXN0ZWQgdGhpcyBvbiB0d28gSW50ZWwgQnJvYWR3ZWxs IG1hY2hpbmVzLgo+IFNpbmNlIGJ5IG5vdyBhbGwgd2UgaGF2ZSBhcmUgaW5kaWNhdGlvbnMgdGhh dCB0aGlzIGlzIGFuIGVycmF0dW0sCj4gdGhpcyBpbmZvcm1hdGlvbiBiZWxvbmdzIGludG8gdGhl IGNvbW1pdCBtZXNzYWdlLiBBcyBpdCBpcyB3cml0dGVuCj4gbm93LCBpdCBtZWFucyB0aGUgYml0 IGNhbid0IGJlIHNldCBvbiBhbnkgaGFyZHdhcmUuIElmIHRoZXJlIGFyZQo+IHJlYXNvbnMgYmV5 b25kIHRoaXMgZXJyYXR1bSB0byB1bmlmb3JtbHkgZGlzYWxsb3cgdGhlIGJpdCB0byBiZQo+IHNl dCBieSBndWVzdHMsIHRoZXNlIHNob3VsZCBiZSBuYW1lZCBoZXJlIHRvby4gQWZ0ZXIgYWxsIHRo ZQo+IHdheSB5b3UgZG8gdGhlIGNoYW5nZSwgeW91IG5vdyByZWZ1c2UgdmFsdWVzIHdpdGggdGhl IGJpdCBzZXQKPiBldmVyeXdoZXJlLgoKSSBkb24ndCB0aGluayB0aGlzIGlzIHNwZWNpZmljIHRv IEJyb2Fkd2VsbC4gSSB0cmllZCB0aGlzIG9uIGEgSGFzd2VsbAoobW9kZWwgNjApIGFuZCBnb3Qg YSAjR1BGIGFzIHdlbGwuCgpJZiBJIHVuZGVyc3RhbmQgd2hhdCB0aGlzIGJpdCBkb2VzLCBpdCBp cyBwcmV0dHkgcG9pbnRsZXNzIGluIGEgZ3Vlc3QuCkl0IGlzIG9ubHkgdXNlZnVsIGluIHNvbWUg c29ydCBvZiBlbWJlZGRlZCBzZXR1cCwgd2hlcmUgc29tZXRoaW5nIGlzCmhvb2tlZCB1cCB0byBh IHBhcnRpY3VsYXIgcGluIG9uIHRoZSBib2FyZC4gU28gcGVyaGFwcyB0aGlzIGlzIG5vdCBhbgpl cnJhdHVtIGJ1dCByYXRoZXIgYSBub3QgZnVsbHkgZG9jdW1lbnRlZCBmZWF0dXJlLCB3aGVyZSBp ZiBub3RoaW5nIGlzCmNvbm5lY3RlZCB0byB0aGF0IHBpbiB0aGlzIGJpdCBzaG91bGQgbm90IGJl IHNldC4KCk9yIG1heWJlIGl0IGlzIGRvY3VtZW50ZWQgYnV0IEkgY2FuJ3QgZmluZCBhbnl0aGlu ZyBvbiB0aGF0LiBFaXRoZXIgd2F5LAp3ZSBzaG91bGQgbWFzayB0aGlzIGJpdC4KCmJvcmlzCgpf X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fXwpYZW4tZGV2ZWwg bWFpbGluZyBsaXN0Clhlbi1kZXZlbEBsaXN0cy54ZW4ub3JnCmh0dHBzOi8vbGlzdHMueGVuLm9y Zy94ZW4tZGV2ZWwK