Re: [PATCH v4 1/9] arm/mem_access: Add (TCR_|TTBCR_)* defines

[Julien Grall <julien.grall@arm.com>]

Hi Sergej,

On 20/06/17 21:33, Sergej Proskurin wrote:
> This commit adds (TCR_|TTBCR_)* defines to simplify access to the
> respective register contents. At the same time, we adjust the macro
> TCR_T0SZ by using the newly introduced TCR_T0SZ_SHIFT instead of the
> hardcoded value.
>
> Signed-off-by: Sergej Proskurin <proskurin@sec.in.tum.de>
> ---
> Cc: Stefano Stabellini <sstabellini@kernel.org>
> Cc: Julien Grall <julien.grall@arm.com>
> ---
> v2: Define TCR_SZ_MASK in a way so that it can be also applied to 32-bit guests
>     using the long-descriptor translation table format.
>
>     Extend the previous commit by further defines allowing a simplified access
>     to the registers TCR_EL1 and TTBCR.
>
> v3: Replace the hardcoded value 0 in the TCR_T0SZ macro with the newly
>     introduced TCR_T0SZ_SHIFT. Also, replace the hardcoded value 14 in
>     the TCR_TG0_* macros with the introduced TCR_TG0_SHIFT.
>
>     Comment when to apply the defines TTBCR_PD(0|1), according to ARM
>     DDI 0487B.a and ARM DDI 0406C.b.
>
>     Remove TCR_TB_* defines.
>
>     Comment when certain TCR_EL2 register fields can be applied.
>
> v4: Cosmetic changes.
> ---
>  xen/include/asm-arm/processor.h | 69 ++++++++++++++++++++++++++++++++++++++---
>  1 file changed, 65 insertions(+), 4 deletions(-)
>
> diff --git a/xen/include/asm-arm/processor.h b/xen/include/asm-arm/processor.h
> index 855ded1b07..863a569432 100644
> --- a/xen/include/asm-arm/processor.h
> +++ b/xen/include/asm-arm/processor.h
> @@ -94,6 +94,13 @@
>  #define TTBCR_N_2KB  _AC(0x03,U)
>  #define TTBCR_N_1KB  _AC(0x04,U)
>
> +/*
> + * TTBCR_PD(0|1) can be applied only if LPAE is disabled, i.e., TTBCR.EAE==0
> + * (ARM DDI 0487B.a G6-5203 and ARM DDI 0406C.b B4-1722).
> + */
> +#define TTBCR_PD0       (_AC(1,U)<<4)
> +#define TTBCR_PD1       (_AC(1,U)<<5)
> +
>  /* SCTLR System Control Register. */
>  /* HSCTLR is a subset of this. */
>  #define SCTLR_TE        (_AC(1,U)<<30)
> @@ -154,7 +161,20 @@
>
>  /* TCR: Stage 1 Translation Control */
>
> -#define TCR_T0SZ(x)     ((x)<<0)
> +#define TCR_T0SZ_SHIFT  (0)
> +#define TCR_T1SZ_SHIFT  (16)
> +#define TCR_T0SZ(x)     ((x)<<TCR_T0SZ_SHIFT)
> +
> +/*
> + * According to ARM DDI 0487B.a, TCR_EL1.{T0SZ,T1SZ} (AArch64, Section D7-2480)
> + * comprises 6 bits and TTBCR.{T0SZ,T1SZ} (AArch32, Section G6-5204) comprises
> + * 3 bits following another 3 bits for RES0. Thus, the mask for both registers
> + * should be 0x3f.
> + */
> +#define TCR_SZ_MASK     (_AC(0x3f,UL)<<0)

Based on your comment above, I don't understand why you are shifting by 
0 here.

> +
> +#define TCR_EPD0        (_AC(0x1,UL)<<7)
> +#define TCR_EPD1        (_AC(0x1,UL)<<23)
>
>  #define TCR_IRGN0_NC    (_AC(0x0,UL)<<8)
>  #define TCR_IRGN0_WBWA  (_AC(0x1,UL)<<8)
> @@ -170,9 +190,50 @@
>  #define TCR_SH0_OS      (_AC(0x2,UL)<<12)
>  #define TCR_SH0_IS      (_AC(0x3,UL)<<12)
>
> -#define TCR_TG0_4K      (_AC(0x0,UL)<<14)
> -#define TCR_TG0_64K     (_AC(0x1,UL)<<14)
> -#define TCR_TG0_16K     (_AC(0x2,UL)<<14)

We are trying to avoid code clean-up and addition in the same patch. I 
am OK with that patch, but you need to mention it in the commit message.

> +/* Note that the fields TCR_EL1.{TG0,TG1} are not available on AArch32. */
> +#define TCR_TG0_SHIFT   (14)
> +#define TCR_TG0_MASK    (_AC(0x3,UL)<<TCR_TG0_SHIFT)
> +#define TCR_TG0_4K      (_AC(0x0,UL)<<TCR_TG0_SHIFT)
> +#define TCR_TG0_64K     (_AC(0x1,UL)<<TCR_TG0_SHIFT)
> +#define TCR_TG0_16K     (_AC(0x2,UL)<<TCR_TG0_SHIFT)
> +
> +/* Note that the field TCR_EL2.TG1 exists only if HCR_EL2.E2H==1. */
> +#define TCR_EL1_TG1_SHIFT   (30)
> +#define TCR_EL1_TG1_MASK    (_AC(0x3,UL)<<TCR_EL1_TG1_SHIFT)
> +#define TCR_EL1_TG1_16K     (_AC(0x1,UL)<<TCR_EL1_TG1_SHIFT)
> +#define TCR_EL1_TG1_4K      (_AC(0x2,UL)<<TCR_EL1_TG1_SHIFT)
> +#define TCR_EL1_TG1_64K     (_AC(0x3,UL)<<TCR_EL1_TG1_SHIFT)
> +
> +/*
> + * Note that the field TCR_EL1.IPS is not available on AArch32. Also, the field
> + * TCR_EL2.IPS exists only if HCR_EL2.E2H==1.
> + */
> +#define TCR_EL1_IPS_SHIFT   (32)
> +#define TCR_EL1_IPS_MASK    (_AC(0x7,ULL)<<TCR_EL1_IPS_SHIFT)
> +#define TCR_EL1_IPS_32_BIT  (_AC(0x0,ULL)<<TCR_EL1_IPS_SHIFT)
> +#define TCR_EL1_IPS_36_BIT  (_AC(0x1,ULL)<<TCR_EL1_IPS_SHIFT)
> +#define TCR_EL1_IPS_40_BIT  (_AC(0x2,ULL)<<TCR_EL1_IPS_SHIFT)
> +#define TCR_EL1_IPS_42_BIT  (_AC(0x3,ULL)<<TCR_EL1_IPS_SHIFT)
> +#define TCR_EL1_IPS_44_BIT  (_AC(0x4,ULL)<<TCR_EL1_IPS_SHIFT)
> +#define TCR_EL1_IPS_48_BIT  (_AC(0x5,ULL)<<TCR_EL1_IPS_SHIFT)
> +#define TCR_EL1_IPS_52_BIT  (_AC(0x6,ULL)<<TCR_EL1_IPS_SHIFT)
> +
> +/*
> + * The following values correspond to the bit masks represented by
> + * TCR_EL1_IPS_XX_BIT defines.
> + */
> +#define TCR_EL1_IPS_32_BIT_VAL  (32)
> +#define TCR_EL1_IPS_36_BIT_VAL  (36)
> +#define TCR_EL1_IPS_40_BIT_VAL  (40)
> +#define TCR_EL1_IPS_42_BIT_VAL  (42)
> +#define TCR_EL1_IPS_44_BIT_VAL  (44)
> +#define TCR_EL1_IPS_48_BIT_VAL  (48)
> +#define TCR_EL1_IPS_52_BIT_VAL  (52)
> +#define TCR_EL1_IPS_MIN_VAL     (25)
> +
> +/* Note that the fields TCR_EL2.TBI(0|1) exist only if HCR_EL2.E2H==1. */
> +#define TCR_EL1_TBI0    (_AC(0x1,ULL)<<37)
> +#define TCR_EL1_TBI1    (_AC(0x1,ULL)<<38)
>
>  #ifdef CONFIG_ARM_64
>
>

Cheers,

-- 
Julien Grall

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