From: Julien Grall <julien.grall@arm.com>
To: Peng Fan <van.freenix@gmail.com>,
Stefano Stabellini <sstabellini@kernel.org>
Cc: xen-devel@lists.xen.org
Subject: Re: [PATCH v4 0/7] unsafe big.LITTLE support
Date: Thu, 8 Mar 2018 11:03:57 +0000 [thread overview]
Message-ID: <edbc8066-397f-9aea-264b-3e27d052b56e@arm.com> (raw)
In-Reply-To: <20180308061458.GA25007@shlinux2>
Hello,
On 08/03/18 06:15, Peng Fan wrote:
> Hi Stefano,
> On Fri, Mar 02, 2018 at 11:05:54AM -0800, Stefano Stabellini wrote:
>> Hi all,
>>
>> This series changes the initialization of two virtual registers to make
>> sure they match the value of the underlying physical cpu.
>>
>> It also disables cpus different from the boot cpu, unless a newly
>> introduced command line option is specified. In that case, it explains
>> how to setup the system to avoid corruptions, which involves manually
>> specifying the cpu affinity of all domains, because the scheduler still
>> lacks big.LITTLE support.
>>
>> In the uncommon case of a system where the cacheline sizes are different
>> across cores, it disables all cores that have a different dcache line size
>>from the boot cpu. In fact, it is not sufficient to use the dcache line
>> size of the current cpu, it would be necessary to use the minimum across
>> all dcache line sizes of all cores. Given that it is actually uncommon
>> even in big.LITTLE systems, just disable cpus for now.
>>
>> The first patch in the series is a fix for the way we read the dcache
>> line size.
>
> I am trying the patchset, but I meet issue that Guest Big/Little with
> vcpu not working properly. As my current hardware has an issue
> which has fix in Kernel, https://source.codeaurora.org/external/imx/linux-imx/commit/?h=imx_4.9.51_imx8_beta2&id=917cc3a8db2f3609ef8e2f59e7bcd31aa2cd4e59
Can you describe what you mean by not working properly? Also what is
your setup? Did you pin the different vCPUs as requested by the
documentation.
>
> I am not sure whether this issue cause DomU big/Little not work.
Well, I would recommend to speak with NXP whether this errata affects
TLB flush for Hypervisor Page-Table or Stage-2 Page-Table.
> So wonder has this patchset been tested on Big/Little Hardware?
This series only adds facility to report the correct MIDR to the guest.
If your platform requires more, then it would be necessary send a patch
for Xen.
Cheers,
--
Julien Grall
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next prev parent reply other threads:[~2018-03-08 11:03 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-03-02 19:05 [PATCH v4 0/7] unsafe big.LITTLE support Stefano Stabellini
2018-03-02 19:06 ` [PATCH v4 1/7] xen/arm: Read the dcache line size from CTR register Stefano Stabellini
2018-03-02 19:06 ` [PATCH v4 2/7] xen/arm: Park CPUs with a MIDR different from the boot CPU Stefano Stabellini
2018-03-02 19:06 ` [PATCH v4 3/7] xen/arm: make processor a per cpu variable Stefano Stabellini
2018-03-02 19:06 ` [PATCH v4 4/7] xen/arm: read ACTLR on the pcpu where the vcpu will run Stefano Stabellini
2018-03-02 19:06 ` [PATCH v4 5/7] xen/arm: set VPIDR based on the MIDR value of the underlying pCPU Stefano Stabellini
2018-03-02 19:06 ` [PATCH v4 6/7] xen/arm: update the docs about heterogeneous computing Stefano Stabellini
2018-03-02 19:06 ` [PATCH v4 7/7] xen/arm: disable CPUs with different dcache line sizes Stefano Stabellini
2018-03-06 10:59 ` Julien Grall
2018-03-06 19:41 ` Stefano Stabellini
2018-03-06 10:46 ` [PATCH v4 1/7] xen/arm: Read the dcache line size from CTR register Julien Grall
2018-03-08 6:15 ` [PATCH v4 0/7] unsafe big.LITTLE support Peng Fan
2018-03-08 11:03 ` Julien Grall [this message]
2018-03-08 12:23 ` Peng Fan
2018-03-08 12:30 ` Julien Grall
2018-03-08 12:43 ` Peng Fan
2018-03-08 15:13 ` Julien Grall
2018-03-09 9:05 ` Peng Fan
2018-03-09 10:22 ` Julien Grall
2018-03-09 13:30 ` Peng Fan
2018-03-09 14:40 ` Julien Grall
2018-03-10 1:09 ` Stefano Stabellini
2018-03-12 2:57 ` Peng Fan
2018-03-12 11:02 ` Julien Grall
2018-03-12 2:32 ` Peng Fan
2018-03-12 10:34 ` Julien Grall
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