From: Julien Grall <julien.grall@linaro.org>
To: Andre Przywara <andre.przywara@linaro.org>,
Stefano Stabellini <sstabellini@kernel.org>,
Manish Jaggi <manish.jaggi@linaro.org>
Cc: xen-devel@lists.xenproject.org
Subject: Re: [PATCH] arm64: ITS: fix cacheability adjustment
Date: Tue, 28 Nov 2017 19:01:14 +0000 [thread overview]
Message-ID: <f5e1eebe-82ba-06c1-27cb-eeae54e4a087@linaro.org> (raw)
In-Reply-To: <541ca3dc-1cb6-f1e4-6355-3e2a59812604@linaro.org>
On 11/28/2017 02:05 PM, Andre Przywara wrote:
> Hi,
Hi Andre,
Sorry someone I skipped that patch :/.
> On 16/11/17 12:02, Andre Przywara wrote:
>> If the host GICv3 redistributor reports that the pending table cannot
>> use shareable memory, we try to drop the cacheability attributes as
>> well. However we fail horribly in doing computer science 101 bit
>> masking, effectively clearing the whole register instead of just a few
>> bits.
>> Fix this by removing the one redundant masking operation and adding the
>> magic negation for the actually needed other operation.
>>
>> Reported-by: Manish Jaggi <manish.jaggi@linaro.org>
>
> Manish, can you please test this patch and confirm that it works?
> Also how does the bug manifest for you?
>
> Julien, Stefano: Are there any objections against taking this patch for > 4.10? This was introduced with the ITS emulation.
Reviewed-by: Julien Grall <julien.grall@linaro.org>
This is new code and in technical preview. So I think it is fine to get
them in Xen 4.10.
Release-Acked-by: Julien Grall <julien.grall@linaro.org>
Cheers,
--
Julien Grall
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prev parent reply other threads:[~2017-11-28 19:01 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-11-16 12:02 [PATCH] arm64: ITS: fix cacheability adjustment Andre Przywara
2017-11-28 14:05 ` Andre Przywara
2017-11-28 19:01 ` Julien Grall [this message]
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