From: Julien Grall <julien.grall@linaro.org>
To: Stefano Stabellini <sstabellini@kernel.org>, xen-devel@lists.xen.org
Cc: julien.grall@arm.com
Subject: Re: [PATCH v2] arm: configure interrupts to be in non-secure group1
Date: Thu, 19 Oct 2017 12:03:11 +0100 [thread overview]
Message-ID: <f62f1548-4a28-cf6d-703f-07fb2baadbf9@linaro.org> (raw)
In-Reply-To: <alpine.DEB.2.10.1710181427250.27209@sstabellini-ThinkPad-X260>
Hi Stefano,
On 18/10/17 22:29, Stefano Stabellini wrote:
> Xen uses non-secure group1 interrupts, however it doesn't configure the
> GICv3 accordingly. Xen needs to set GICD_IGROUPR for SPIs and
> GICR_IGROUPR0 for local interrupt to "1" to specify that interrupts
> belong to group1. This is particularly important if the system has
> GICD_CTLR.DS set, also see commit
> 7c9b973061b03af62734f613f6abec46c0dd4a88 in Linux.
>
> Signed-off-by: Stefano Stabellini <sstabellini@kernel.org>
Reviewed-by: Julien Grall <julien.grall@linaro.org>
Released-acked-by: Julien Grall <julien.grall@linaro.org>
Cheers,
>
> ---
>
> This is a candidate for stable backports.
>
> diff --git a/xen/arch/arm/gic-v3.c b/xen/arch/arm/gic-v3.c
> index 74d00e0..77da892 100644
> --- a/xen/arch/arm/gic-v3.c
> +++ b/xen/arch/arm/gic-v3.c
> @@ -569,6 +569,13 @@ static void __init gicv3_dist_init(void)
> for ( i = NR_GIC_LOCAL_IRQS; i < nr_lines; i += 32 )
> writel_relaxed(0xffffffff, GICD + GICD_ICENABLER + (i / 32) * 4);
>
> + /*
> + * Configure SPIs as non-secure Group-1. This will only matter
> + * if the GIC only has a single security state.
> + */
> + for ( i = NR_GIC_LOCAL_IRQS; i < nr_lines; i += 32 )
> + writel_relaxed(GENMASK(31, 0), GICD + GICD_IGROUPR + (i / 32) * 4);
> +
> gicv3_dist_wait_for_rwp();
>
> /* Turn on the distributor */
> @@ -775,6 +782,8 @@ static int gicv3_cpu_init(void)
> */
> writel_relaxed(0xffff0000, GICD_RDIST_SGI_BASE + GICR_ICENABLER0);
> writel_relaxed(0x0000ffff, GICD_RDIST_SGI_BASE + GICR_ISENABLER0);
> + /* Configure SGIs/PPIs as non-secure Group-1 */
> + writel_relaxed(GENMASK(31, 0), GICD_RDIST_SGI_BASE + GICR_IGROUPR0);
>
> gicv3_redist_wait_for_rwp();
>
>
> _______________________________________________
> Xen-devel mailing list
> Xen-devel@lists.xen.org
> https://lists.xen.org/xen-devel
>
--
Julien Grall
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Xen-devel@lists.xen.org
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next prev parent reply other threads:[~2017-10-19 11:03 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-10-18 21:29 [PATCH v2] arm: configure interrupts to be in non-secure group1 Stefano Stabellini
2017-10-19 11:03 ` Julien Grall [this message]
2017-10-20 8:37 ` Andre Przywara
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