From: Julien Grall <julien.grall@arm.com>
To: Manish Jaggi <mjaggi@caviumnetworks.com>,
Manish Jaggi <manish.jaggi@cavium.com>,
xen-devel@lists.xenproject.org, sstabellini@kernel.org,
marc.zyngier@arm.com, andre.przywara@arm.com
Subject: Re: [PATCH v1 00/15] arm64: Mediate access to GICv3 sysregs at EL2
Date: Wed, 21 Mar 2018 05:02:25 +0000 [thread overview]
Message-ID: <f8a425e2-413f-508b-db36-be589b603ddb@arm.com> (raw)
In-Reply-To: <fa9fcde0-ac40-a950-920e-455815b924c7@caviumnetworks.com>
On 03/21/2018 04:58 AM, Manish Jaggi wrote:
>
> Hi Julien,
>
> On 03/20/2018 01:16 PM, Julien Grall wrote:
>>
>>
>> On 03/16/2018 11:58 AM, Manish Jaggi wrote:
>>> This patchset is a Xen port of Marc's patchset.
>>> arm64: KVM: Mediate access to GICv3 sysregs at EL2 [1]
>>>
>>> The current RFC patchset is a subset of [1], as it handleing only
>>> Group1 traps
>>> as a PoC. Most of the trap code is added in vsysreg.c. Trap handler
>>> function is kept
>>> independent of the usual guest trap handling code.
>>> Looking for feedback on this approach.
>>
>> This cover letter does not seem to match the series. Please update it
>> on every time you send a series.
> %s/vsysreg.c/vgic-v3-sr..
"The current RFC patchset is a subset of [1], as it handling only Group
1 traps as a PoC". This is clearly not a PoC anymore nor only handling
Group 1.
>
> Could you please review the other patches in the series, so that I can
> send v2.
It is in my queue of patch to review.
Cheers,
--
Julien Grall
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next prev parent reply other threads:[~2018-03-21 5:02 UTC|newest]
Thread overview: 37+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-03-16 11:58 [PATCH v1 00/15] arm64: Mediate access to GICv3 sysregs at EL2 Manish Jaggi
2018-03-16 11:58 ` [PATCH v1 01/15] arm64: cputype: Add MIDR values for Cavium ThunderX1 CPU family Manish Jaggi
2018-03-20 7:38 ` Julien Grall
2018-03-16 11:58 ` [PATCH v1 02/15] arm64: Add config for Cavium Thunder erratum 30115 Manish Jaggi
2018-03-20 7:43 ` Julien Grall
2018-03-21 5:06 ` Manish Jaggi
2018-03-21 7:49 ` Julien Grall
2018-03-16 11:58 ` [PATCH v1 03/15] arm: Placeholder for handling Group0/1 traps for Cavium Erratum 30115 Manish Jaggi
2018-03-20 8:08 ` Julien Grall
2018-03-16 11:58 ` [PATCH v1 04/15] arm64: vgic-v3: Add ICV_BPR1_EL1 handler Manish Jaggi
2018-03-21 8:11 ` Julien Grall
2018-03-26 13:11 ` Manish Jaggi
2018-03-16 11:58 ` [PATCH v1 05/15] arm64: vgic-v3: Add ICV_IGRPEN1_EL1 handler Manish Jaggi
2018-03-21 8:38 ` Julien Grall
2018-03-26 13:09 ` Manish Jaggi
2018-03-16 11:58 ` [PATCH v1 06/15] arm64: Add accessors for the ICH_APxRn_EL2 registers Manish Jaggi
2018-03-26 13:19 ` Manish Jaggi
2018-03-26 14:36 ` Marc Zyngier
2018-03-16 11:58 ` [PATCH v1 07/15] Expose ich_read/write_lr in vgic-v3-sr.c Manish Jaggi
2018-03-16 11:58 ` [PATCH v1 08/15] arm64: Add ICV_IAR1_EL1 handler Manish Jaggi
2018-03-16 11:58 ` [PATCH v1 09/15] arm64: vgic-v3: Add ICV_EOIR1_EL1 handler Manish Jaggi
2018-03-16 11:58 ` [PATCH v1 10/15] arm64: vgic-v3: Add ICV_HPPIR1_EL1 handler Manish Jaggi
2018-03-16 11:58 ` [PATCH v1 11/15] arm64: vgic-v3: Add ICV_BPR0_EL1 handler Manish Jaggi
2018-03-16 11:58 ` [PATCH v1 12/15] arm64: vgic-v3: Add ICV_IGNREN0_EL1 handler Manish Jaggi
2018-03-16 11:58 ` [PATCH v1 13/15] arm64: vgic-v3: Add misc Group-0 handlers Manish Jaggi
2018-03-16 11:58 ` [PATCH v1 14/15] arm64: vgic-v3: Add ICV_AP(0/1)Rn_EL1 handler Manish Jaggi
2018-03-16 11:58 ` [PATCH v1 15/15] Enable Group0/1 Traps by default for Cavium ThunderX1 Manish Jaggi
2018-03-20 7:46 ` [PATCH v1 00/15] arm64: Mediate access to GICv3 sysregs at EL2 Julien Grall
2018-03-21 4:58 ` Manish Jaggi
2018-03-21 5:02 ` Julien Grall [this message]
2018-03-21 8:45 ` Julien Grall
2018-03-21 9:38 ` Manish Jaggi
2018-03-21 9:56 ` Julien Grall
2018-03-23 6:42 ` Manish Jaggi
2018-03-23 6:58 ` Julien Grall
2018-03-26 4:43 ` Manish Jaggi
2018-03-26 8:24 ` Marc Zyngier
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