From: Julien Grall <julien.grall@arm.com>
To: Andre Przywara <andre.przywara@arm.com>,
Stefano Stabellini <sstabellini@kernel.org>
Cc: xen-devel@lists.xenproject.org,
Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com>,
Vijay Kilari <vijay.kilari@gmail.com>,
Shanker Donthineni <shankerd@codeaurora.org>
Subject: Re: [PATCH v8 03/27] ARM: GIC: Add checks for NULL pointer pending_irq's
Date: Wed, 12 Apr 2017 15:52:28 +0100 [thread overview]
Message-ID: <fdf1e1c7-3aff-3149-c089-33db2c13d79e@arm.com> (raw)
In-Reply-To: <114e3aff-65e0-7794-e1ef-68c62be70832@arm.com>
On 12/04/17 15:51, Andre Przywara wrote:
> Hi,
>
> On 12/04/17 11:25, Julien Grall wrote:
>> Hi Andre,
>>
>> On 12/04/17 01:44, Andre Przywara wrote:
>>> For LPIs the struct pending_irq's are dynamically allocated and the
>>> pointers will be stored in a radix tree. Since an LPI can be "unmapped"
>>> at any time, teach the VGIC how to handle with irq_to_pending() returning
>>> a NULL pointer.
>>> We just do nothing in this case or clean up the LR if the virtual LPI
>>> number was still in an LR.
>>
>> Why not all the irq_to_pending call are not protected (such as
>> vgic_irq_to_migrate)?
>
> Some of them are never called by LPIs.
> Is it worth the put ASSERTs in there everywhere?
Yes.
> I can copy the table with all call sites and their evaluations from that
> other email into this commit message, if that sounds good.
And yes. A commit message should contain all the details saving us time
to look in the e-mails...
>
> Fixed the rest.
>
> Cheers,
> Andre.
>
>> This is a call to forget to check NULL if we
>> decide to use the function in the future.
>>
>> Also, I would like a comment on top of irq_to_pending stating this can
>> return NULL as you change the semantic of the function.
>>>
>>> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
>>> ---
>>> xen/arch/arm/gic.c | 37 ++++++++++++++++++++++++++++++++-----
>>> xen/arch/arm/vgic.c | 6 ++++++
>>> 2 files changed, 38 insertions(+), 5 deletions(-)
>>>
>>> diff --git a/xen/arch/arm/gic.c b/xen/arch/arm/gic.c
>>> index dcb1783..62ae3b8 100644
>>> --- a/xen/arch/arm/gic.c
>>> +++ b/xen/arch/arm/gic.c
>>> @@ -408,9 +408,15 @@ void gic_remove_from_queues(struct vcpu *v,
>>> unsigned int virtual_irq)
>>> spin_lock_irqsave(&v->arch.vgic.lock, flags);
>>>
>>> p = irq_to_pending(v, virtual_irq);
>>> -
>>> - if ( !list_empty(&p->lr_queue) )
>>> - list_del_init(&p->lr_queue);
>>> + /*
>>> + * If an LPIs has been removed meanwhile, it has been cleaned up
>>> + * already, so nothing to remove here.
>>> + */
>>> + if ( p )
>>> + {
>>> + if ( !list_empty(&p->lr_queue) )
>>> + list_del_init(&p->lr_queue);
>>> + }
>>
>> This could be simplified with:
>>
>> if ( p && !list_empty(&p->lr_queue) )
>> list_del_init(...);
>>
>> Also, you probably want a likely(p).
>>
>>> spin_unlock_irqrestore(&v->arch.vgic.lock, flags);
>>> }
>>>
>>> @@ -418,6 +424,10 @@ void gic_raise_inflight_irq(struct vcpu *v,
>>> unsigned int virtual_irq)
>>> {
>>> struct pending_irq *n = irq_to_pending(v, virtual_irq);
>>>
>>> + /* If an LPI has been removed meanwhile, there is nothing left to
>>> raise. */
>>> + if ( !n )
>>
>> if ( unlikely(!n) )
>>
>>> + return;
>>> +
>>> ASSERT(spin_is_locked(&v->arch.vgic.lock));
>>>
>>> if ( list_empty(&n->lr_queue) )
>>> @@ -437,6 +447,11 @@ void gic_raise_guest_irq(struct vcpu *v, unsigned
>>> int virtual_irq,
>>> {
>>> int i;
>>> unsigned int nr_lrs = gic_hw_ops->info->nr_lrs;
>>> + struct pending_irq *p = irq_to_pending(v, virtual_irq);
>>> +
>>> + if ( !p )
>>
>> if ( unlikely(!p) )
>>
>>> + /* An unmapped LPI does not need to be raised. */
>>> + return;
>>
>> Please move this check after the ASSERT to keep the check on all the paths.
>>
>>>
>>> ASSERT(spin_is_locked(&v->arch.vgic.lock));
>>>
>>> @@ -445,12 +460,12 @@ void gic_raise_guest_irq(struct vcpu *v,
>>> unsigned int virtual_irq,
>>> i = find_first_zero_bit(&this_cpu(lr_mask), nr_lrs);
>>> if (i < nr_lrs) {
>>> set_bit(i, &this_cpu(lr_mask));
>>> - gic_set_lr(i, irq_to_pending(v, virtual_irq),
>>> GICH_LR_PENDING);
>>> + gic_set_lr(i, p, GICH_LR_PENDING);
>>> return;
>>> }
>>> }
>>>
>>> - gic_add_to_lr_pending(v, irq_to_pending(v, virtual_irq));
>>> + gic_add_to_lr_pending(v, p);
>>> }
>>>
>>> static void gic_update_one_lr(struct vcpu *v, int i)
>>> @@ -464,7 +479,19 @@ static void gic_update_one_lr(struct vcpu *v, int i)
>>>
>>> gic_hw_ops->read_lr(i, &lr_val);
>>> irq = lr_val.virq;
>>> +
>>
>> 4th time I am saying this.... Spurious line.
>>
>>> p = irq_to_pending(v, irq);
>>> + /* An LPI might have been unmapped, in which case we just clean
>>> up here. */
>>> + if ( !p )
>>
>> unlikely(!p)
>>
>>> + {
>>> + ASSERT(is_lpi(irq));
>>> +
>>> + gic_hw_ops->clear_lr(i);
>>> + clear_bit(i, &this_cpu(lr_mask));
>>> +
>>> + return;
>>> + }
>>> +
>>> if ( lr_val.state & GICH_LR_ACTIVE )
>>> {
>>> set_bit(GIC_IRQ_GUEST_ACTIVE, &p->status);
>>> diff --git a/xen/arch/arm/vgic.c b/xen/arch/arm/vgic.c
>>> index c953f13..b9fc837 100644
>>> --- a/xen/arch/arm/vgic.c
>>> +++ b/xen/arch/arm/vgic.c
>>> @@ -473,6 +473,12 @@ void vgic_vcpu_inject_irq(struct vcpu *v,
>>> unsigned int virq)
>>> spin_lock_irqsave(&v->arch.vgic.lock, flags);
>>>
>>> n = irq_to_pending(v, virq);
>>> + /* If an LPI has been removed, there is nothing to inject here. */
>>> + if ( !n )
>>
>> unlikely(...)
>>
>>> + {
>>> + spin_unlock_irqrestore(&v->arch.vgic.lock, flags);
>>> + return;
>>> + }
>>>
>>> priority = vgic_get_virq_priority(v, virq);
>>>
>>>
>>
>> Cheers,
>>
--
Julien Grall
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next prev parent reply other threads:[~2017-04-12 14:52 UTC|newest]
Thread overview: 82+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-04-12 0:44 [PATCH v8 00/27] arm64: Dom0 ITS emulation Andre Przywara
2017-04-12 0:44 ` [PATCH v8 01/27] ARM: GICv3: propagate number of host LPIs to GICv3 guest Andre Przywara
2017-04-12 10:06 ` Julien Grall
2017-04-12 0:44 ` [PATCH v8 02/27] ARM: VGIC: move irq_to_pending() calls under the VGIC VCPU lock Andre Przywara
2017-04-12 10:13 ` Julien Grall
2017-04-12 11:38 ` Julien Grall
2017-04-12 0:44 ` [PATCH v8 03/27] ARM: GIC: Add checks for NULL pointer pending_irq's Andre Przywara
2017-04-12 10:25 ` Julien Grall
2017-04-12 14:51 ` Andre Przywara
2017-04-12 14:52 ` Julien Grall [this message]
2017-04-12 0:44 ` [PATCH v8 04/27] ARM: GICv3: introduce separate pending_irq structs for LPIs Andre Przywara
2017-04-12 10:35 ` Julien Grall
2017-04-12 0:44 ` [PATCH v8 05/27] ARM: GICv3: forward pending LPIs to guests Andre Przywara
2017-04-12 10:44 ` Julien Grall
2017-04-12 17:26 ` Andre Przywara
2017-05-10 10:47 ` Andre Przywara
2017-05-10 11:07 ` Julien Grall
2017-05-10 17:14 ` Andre Przywara
2017-05-10 17:17 ` Julien Grall
2017-05-11 17:55 ` Andre Przywara
2017-04-12 0:44 ` [PATCH v8 06/27] ARM: GICv3: enable ITS and LPIs on the host Andre Przywara
2017-04-12 0:44 ` [PATCH v8 07/27] ARM: vGICv3: handle virtual LPI pending and property tables Andre Przywara
2017-04-12 10:55 ` Julien Grall
2017-04-12 13:12 ` Andre Przywara
2017-04-12 13:13 ` Julien Grall
2017-05-11 17:54 ` Andre Przywara
2017-04-12 0:44 ` [PATCH v8 08/27] ARM: introduce vgic_access_guest_memory() Andre Przywara
2017-04-12 12:29 ` Julien Grall
2017-04-12 0:44 ` [PATCH v8 09/27] ARM: vGICv3: re-use vgic_reg64_check_access Andre Przywara
2017-04-12 0:44 ` [PATCH v8 10/27] ARM: GIC: export vgic_init_pending_irq() Andre Przywara
2017-04-12 0:44 ` [PATCH v8 11/27] ARM: VGIC: add vcpu_id to struct pending_irq Andre Przywara
2017-04-12 12:32 ` Julien Grall
2017-04-12 12:37 ` Andre Przywara
2017-04-12 0:44 ` [PATCH v8 12/27] ARM: vGIC: advertise LPI support Andre Przywara
2017-04-12 12:38 ` Julien Grall
2017-04-12 12:48 ` Andre Przywara
2017-04-12 13:04 ` Julien Grall
2017-04-12 0:44 ` [PATCH v8 13/27] ARM: vITS: add command handling stub and MMIO emulation Andre Przywara
2017-04-12 12:59 ` Julien Grall
2017-04-12 0:44 ` [PATCH v8 14/27] ARM: vITS: introduce translation table walks Andre Przywara
2017-04-12 13:22 ` Julien Grall
2017-04-12 13:36 ` Andre Przywara
2017-04-12 13:37 ` Julien Grall
2017-04-12 0:44 ` [PATCH v8 15/27] ARM: vITS: handle CLEAR command Andre Przywara
2017-04-12 14:10 ` Julien Grall
2017-04-12 14:29 ` Andre Przywara
2017-04-12 14:49 ` Julien Grall
2017-04-12 0:44 ` [PATCH v8 16/27] ARM: vITS: handle INT command Andre Przywara
2017-04-12 14:50 ` Julien Grall
2017-04-12 0:44 ` [PATCH v8 17/27] ARM: vITS: handle MAPC command Andre Przywara
2017-04-12 14:51 ` Julien Grall
2017-04-12 0:44 ` [PATCH v8 18/27] ARM: vITS: handle MAPD command Andre Przywara
2017-04-12 15:21 ` Julien Grall
2017-04-12 17:03 ` Andre Przywara
2017-04-12 17:05 ` Julien Grall
2017-04-12 17:24 ` Andrew Cooper
2017-04-12 18:18 ` Wei Liu
2017-05-10 10:42 ` Andre Przywara
2017-05-10 11:30 ` Julien Grall
2017-04-12 0:44 ` [PATCH v8 19/27] ARM: vITS: handle MAPTI command Andre Przywara
2017-04-12 16:18 ` Julien Grall
2017-04-12 16:27 ` Andre Przywara
2017-04-12 17:16 ` Julien Grall
2017-04-12 17:25 ` Julien Grall
2017-04-12 0:44 ` [PATCH v8 20/27] ARM: GICv3: handle unmapped LPIs Andre Przywara
2017-04-12 9:46 ` Andre Przywara
2017-04-12 16:49 ` Julien Grall
2017-04-12 0:44 ` [PATCH v8 21/27] ARM: vITS: handle MOVI command Andre Przywara
2017-04-12 16:59 ` Julien Grall
2017-05-10 10:34 ` Andre Przywara
2017-04-12 0:44 ` [PATCH v8 22/27] ARM: vITS: handle DISCARD command Andre Przywara
2017-04-12 17:06 ` Julien Grall
2017-04-12 0:44 ` [PATCH v8 23/27] ARM: vITS: handle INV command Andre Przywara
2017-04-12 17:20 ` Julien Grall
2017-05-10 15:11 ` Andre Przywara
2017-05-11 10:43 ` Julien Grall
2017-04-12 0:44 ` [PATCH v8 24/27] ARM: vITS: handle INVALL command Andre Przywara
2017-04-12 17:26 ` Julien Grall
2017-04-12 0:44 ` [PATCH v8 25/27] ARM: vITS: increase mmio_count for each ITS Andre Przywara
2017-04-12 0:44 ` [PATCH v8 26/27] ARM: vITS: create and initialize virtual ITSes for Dom0 Andre Przywara
2017-04-12 0:44 ` [PATCH v8 27/27] ARM: vITS: create ITS subnodes for Dom0 DT Andre Przywara
2017-04-12 14:13 ` [PATCH v8 00/27] arm64: Dom0 ITS emulation Julien Grall
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