* [ovmf test] 103411: regressions - FAIL
@ 2016-12-16 20:28 osstest service owner
0 siblings, 0 replies; only message in thread
From: osstest service owner @ 2016-12-16 20:28 UTC (permalink / raw)
To: xen-devel, osstest-admin
flight 103411 ovmf real [real]
http://logs.test-lab.xenproject.org/osstest/logs/103411/
Regressions :-(
Tests which did not succeed and are blocking,
including tests which could not be run:
test-amd64-i386-xl-qemuu-ovmf-amd64 17 guest-start/debianhvm.repeat fail REGR. vs. 103347
version targeted for testing:
ovmf 16296a126c99174ad27a6d78229df70e62049310
baseline version:
ovmf aaa61995af9e0b65c37bdad6796867760fa1d5fe
Last test of basis 103347 2016-12-14 16:28:50 Z 2 days
Testing same since 103411 2016-12-15 15:56:32 Z 1 days 1 attempts
------------------------------------------------------------
People who touched revisions under test:
Ard Biesheuvel <ard.biesheuvel@linaro.org>
Marcin Wojtas <mw@semihalf.com>
jobs:
build-amd64-xsm pass
build-i386-xsm pass
build-amd64 pass
build-i386 pass
build-amd64-libvirt pass
build-i386-libvirt pass
build-amd64-pvops pass
build-i386-pvops pass
test-amd64-amd64-xl-qemuu-ovmf-amd64 pass
test-amd64-i386-xl-qemuu-ovmf-amd64 fail
------------------------------------------------------------
sg-report-flight on osstest.test-lab.xenproject.org
logs: /home/logs/logs
images: /home/logs/images
Logs, config files, etc. are available at
http://logs.test-lab.xenproject.org/osstest/logs
Explanation of these reports, and of osstest in general, is at
http://xenbits.xen.org/gitweb/?p=osstest.git;a=blob;f=README.email;hb=master
http://xenbits.xen.org/gitweb/?p=osstest.git;a=blob;f=README;hb=master
Test harness code can be found at
http://xenbits.xen.org/gitweb?p=osstest.git;a=summary
Not pushing.
------------------------------------------------------------
commit 16296a126c99174ad27a6d78229df70e62049310
Author: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Date: Fri Dec 9 15:04:34 2016 +0000
MdeModulePkg/NonDiscoverablePciDeviceDxe: add support for non-coherent DMA
Add support for non-coherent DMA, either by performing explicit cache
maintenance when DMA mappings are aligned to the CPU's DMA buffer alignment,
or by bounce buffering via uncached mappings otherwise.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Tested-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
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